| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Big redign of model structures | Suren A. Chilingaryan | 2015-04-20 | 1 | -211/+0 | 
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| * | multithread preprocessing of ipecamera frames and code reorganization | Suren A. Chilingaryan | 2011-12-12 | 1 | -2/+2 | 
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| * | Support dynamic registers, support register offsets and multiregisters ↵ | Suren A. Chilingaryan | 2011-07-09 | 1 | -6/+7 | 
| | | | | | (bitmasks), list NWL DMA registers | ||||
| * | Move to new FPGA design | root | 2011-06-16 | 1 | -4/+4 | 
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| * | Alternative way to overcome problem with address verification of CMOSIS ↵ | Suren A. Chilingaryan | 2011-04-14 | 1 | -24/+26 | 
| | | | | | registers | ||||
| * | Support simplified mode (slow) of writting CMOSIS sensors: issue 3 writes + ↵ | Suren A. Chilingaryan | 2011-04-13 | 1 | -23/+84 | 
| | | | | | delays and when start looking for status | ||||
| * | Infrastructure for event API | Suren A. Chilingaryan | 2011-04-12 | 1 | -0/+147 | 
