Initial integration of XML support

1 files changed, 494 insertions, 0 deletions

diff --git a/xml/test/camera.xml b/xml/test/camera.xml
new file mode 100644
index 0000000..5f803d0
--- /dev/null
+++ b/xml/test/camera.xml
@@ -0,0 +1,494 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+<model xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <banks>
+    <bank>
+      <bank_description>
+        <bar>0</bar>
+        <size>0x0200</size>
+        <protocol>default</protocol>
+        <read_address>0x9000</read_address>
+        <write_address>0x9000</write_address>
+        <word_size>32</word_size>
+        <endianess>little</endianess>
+        <format>0x%lx</format>
+        <name>fpga</name>
+        <description>IPECamera Registers</description>
+      </bank_description>
+      <registers>
+        <register>
+          <address>0x00</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>spi_conf_input</name>
+        </register>
+        <register>
+          <address>0x10</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>spi_conf_output</name>
+        </register>
+        <register>
+          <address>0x20</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>spi_clk_speed</name>
+        </register>
+        <register>
+          <address>0x30</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>firmware_info</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>8</size>
+              <mode>R</mode>
+              <name>firmware_version</name>
+            </register_bits>
+            <register_bits>
+              <offset>8</offset>
+              <size>1</size>
+              <mode>R</mode>
+              <name>firmware_bitmode</name>
+            </register_bits>
+            <register_bits>
+              <offset>12</offset>
+              <size>2</size>
+              <mode>R</mode>
+              <name>adc_resolution</name>
+            </register_bits>
+            <register_bits>
+              <offset>16</offset>
+              <size>2</size>
+              <mode>R</mode>
+              <name>output_mode</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <address>0x40</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>control</name>
+		<registers_bits>
+        	    <register_bits>
+              		<offset>31</offset>
+	                <size>1</size>
+	                <mode>R</mode>
+          	        <name>freq</name>
+            	    </register_bits>
+		</registers_bits>	
+        </register>
+        <register>
+          <address>0x50</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>status</name>
+        </register>
+        <register>
+          <address>0x54</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>status2</name>
+        </register>
+        <register>
+          <address>0x58</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>status3</name>
+        </register>
+        <register>
+          <address>0x5c</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>fr_status</name>
+        </register>
+        <register>
+          <address>0x70</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>start_address</name>
+        </register>
+        <register>
+          <address>0x74</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>end_address</name>
+        </register>
+        <register>
+          <address>0x78</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>rd_address</name>
+        </register>
+        <register>
+          <address>0xa0</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>fr_param1</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>10</size>
+              <mode>RW</mode>
+              <name>fr_skip_lines</name>
+            </register_bits>
+            <register_bits>
+              <offset>10</offset>
+              <size>11</size>
+              <mode>RW</mode>
+              <name>fr_num_lines</name>
+            </register_bits>
+            <register_bits>
+              <offset>21</offset>
+              <size>11</size>
+              <mode>RW</mode>
+              <name>fr_start_address</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <address>0xb0</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>all</rwmask>
+          <mode>RW</mode>
+          <name>fr_param2</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>11</size>
+              <mode>RW</mode>
+              <name>fr_threshold_start_line</name>
+            </register_bits>
+            <register_bits>
+              <offset>16</offset>
+              <size>10</size>
+              <mode>RW</mode>
+              <name>fr_area_lines</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <address>0xc0</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>skiped_lines</name>
+        </register>
+        <register>
+          <address>0xd0</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>all</rwmask>
+          <mode>RW</mode>
+          <name>fr_thresholds</name>
+        </register>
+        <register>
+          <address>0xd0</address>
+          <offset>0</offset>
+          <size>10</size>
+          <default>0</default>
+          <rwmask>all</rwmask>
+          <mode>RW</mode>
+          <name>fr_pixel_thr</name>
+        </register>
+        <register>
+          <address>0xd0</address>
+          <offset>10</offset>
+          <size>11</size>
+          <default>0</default>
+          <rwmask>all</rwmask>
+          <mode>RW</mode>
+          <name>fr_num_pixel_thr</name>
+        </register>
+        <register>
+          <address>0xd0</address>
+          <offset>21</offset>
+          <size>11</size>
+          <default>0</default>
+          <rwmask>all</rwmask>
+          <mode>RW</mode>
+          <name>fr_num_lines_thr</name>
+        </register>
+        <register>
+          <address>0x100</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>rawdata_pkt_addr</name>
+        </register>
+        <register>
+          <address>0x110</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>temperature_info</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>16</size>
+              <mode>R</mode>
+              <name>sensor_temperature</name>
+		<views>
+		<view>formuu1</view>
+		<view>formuu2</view>
+                <view>enumm2</view>
+              </views>
+            </register_bits>
+            <register_bits>
+              <offset>16</offset>
+              <size>3</size>
+              <mode>R</mode>
+              <name>sensor_temperature_alarms</name>
+            </register_bits>
+            <register_bits>
+              <offset>19</offset>
+              <size>10</size>
+              <mode>RW</mode>
+              <name>fpga_temperature</name>
+              <views>
+                <view>formuu1</view>
+                <view>enumm1</view>
+              </views>
+            </register_bits>
+            <register_bits>
+              <offset>29</offset>
+              <size>3</size>
+              <mode>R</mode>
+              <name>fpga_temperature_alarms</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <address>0x120</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>num_lines</name>
+        </register>
+        <register>
+          <address>0x130</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>start_line</name>
+        </register>
+        <register>
+          <address>0x140</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>exp_time</name>
+        </register>
+        <register>
+          <address>0x150</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>motor</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_phi</name>
+            </register_bits>
+            <register_bits>
+              <offset>5</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_z</name>
+            </register_bits>
+            <register_bits>
+              <offset>10</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_y</name>
+            </register_bits>
+            <register_bits>
+              <offset>15</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_x</name>
+            </register_bits>
+            <register_bits>
+              <offset>20</offset>
+              <size>8</size>
+              <mode>R</mode>
+              <name>adc_gain</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <address>0x160</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>write_status</name>
+        </register>
+        <register>
+          <address>0x170</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>num_triggers</name>
+        </register>
+        <register>
+          <address>0x180</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0x280</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>trigger_period</name>
+	  <views>
+		<view>enumm2</view>
+	  </views>
+        </register>
+        <register>
+          <address>0x190</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>temperature_sample_period</name>
+        </register>
+        <register>
+          <address>0x1a0</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0x64</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>ddr_max_frames</name>
+        </register>
+        <register>
+          <address>0x1b0</address>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>ddr_num_frames</name>
+        </register>
+      </registers>
+    </bank>
+    <bank>
+	<bank_description>
+        <bar>0</bar>
+        <size>0x0200</size>
+        <protocol>default</protocol>
+        <read_address>0x0</read_address>
+        <write_address>0x0</write_address>
+        <word_size>32</word_size>
+        <endianess>little</endianess>
+        <format>0x%lx</format>
+        <name>dma</name>
+        <description>DMA Registers</description>
+	</bank_description>
+    </bank>
+  </banks>
+  <views>
+    <view type="formula">
+      <name>formuu1</name>
+	<unit>C</unit>
+      <read_from_register>(503975./1024000)*@reg - 27315./100</read_from_register>
+      <write_to_register>(@value + 27315./100)*(102400./503975)</write_to_register>
+<description>formula to get real fpga temperature from the fpga_temperature register in decimal</description>
+    </view>
+    <view type="enum">
+      <name>enumm1</name>
+      <enum value="0x100" min="0x2" max="0x300">high</enum>
+      <enum value="0x010">low</enum>
+	<description>enum towards temperatures register</description>
+    </view>
+    <view type="formula">
+      <name>formuu2</name>
+	<unit>C</unit>
+      <read_from_register>((1./4)*(@reg - 1200)) if @freq==0 else ((3./10)*(@reg - 1000))</read_from_register>
+      <write_to_register>4*@value + 1200 if @freq==0 else (10./3)*@value + 1000</write_to_register>
+      <description>formula to get real sensor temperature from the sensor_temperature register in decimal</description>
+    </view>
+    <view type="enum">
+      <name>enumm2</name>
+      <enum value="0x120">high</enum>
+      <enum value="0x010" min="0x00" max="0x020">low</enum>
+	   <description>enum towards sensor_temperature register</description>
+    </view>
+    <view type="formula">
+      <name>formuu3</name>
+	<unit>us</unit>  
+      <read_from_register>(@reg+(43./100))*129./(40*1000000)if @freq==0 else (@reg+(43./100))*129./(48*1000000)</read_from_register>
+      <write_to_register>@value/129.*(40*1000000) - 43./100 if @freq==0 else @value/129.*(48*1000000) - 43./100</write_to_register>
+	<description>formula to get real exposure time from the cmosis_exp_time register in decimal</description> 
+    </view>
+    <view type="enum">
+      <name>enumm3</name>
+      <enum  value="0x000">short</enum>
+      <enum  value="0x010">mid</enum>
+      <enum  value="0x100" min="0x0F0">long</enum>
+	<description>enum towards cmosis_exp_register register</description>
+    </view>
+  </views>
+</model>