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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-08-06 05:27:21 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-08-06 05:27:21 +0200 |
| commit | ccbad1cc8eca5f361427dd0ceca15cfa6d68a6d9 (patch) | |
| tree | 0e7e6c1fbf7a22966570062d6ec323cb59ee2a02 /dma/ipe.h | |
| parent | d60dd48eec0ef5d7bf2feca9b3f06374a2f444aa (diff) | |
| download | pcitool-ccbad1cc8eca5f361427dd0ceca15cfa6d68a6d9.tar.gz pcitool-ccbad1cc8eca5f361427dd0ceca15cfa6d68a6d9.tar.bz2 pcitool-ccbad1cc8eca5f361427dd0ceca15cfa6d68a6d9.tar.xz pcitool-ccbad1cc8eca5f361427dd0ceca15cfa6d68a6d9.zip | |
Detect if IPEDMA operates in streaming mode
Diffstat (limited to 'dma/ipe.h')
| -rw-r--r-- | dma/ipe.h | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -65,7 +65,9 @@ static const pcilib_register_description_t ipe_dma_registers[] = { {0x000C, 24, 8, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_up_addr", "Upper address for 64 bit memory addressing"}, {0x0010, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_count", "Write DMA TLP Count"}, {0x0014, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_pattern", "DMA generator data pattern"}, - {0x0018, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "pcie_gen", "PCIe version 2/3 depending on the used XILINX core"}, + {0x0018, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_mode_flags", "DMA operation mode"}, + {0x0018, 0, 4, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "pcie_gen", "PCIe version 2/3 depending on the used XILINX core"}, + {0x0018, 4, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "streaming_dma", "Streaming mode (enabled/disabled)"}, {0x0028, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_perf", "MWR Performance"}, {0x003C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_lnk_width", "Negotiated and max width of PCIe Link"}, {0x003C, 0, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_lnk_width", "Max link width"}, |