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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-04-27 02:28:57 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-04-27 02:28:57 +0200 |
| commit | e1265fa32837f457ee2c2fa259d12c9545af4bbf (patch) | |
| tree | 64b8d5f1c81c14f019047b0cb00cb77c2dcecf55 /dma | |
| parent | a37beb44d59cca329d0d9345c21505af81030688 (diff) | |
| download | ipecamera-e1265fa32837f457ee2c2fa259d12c9545af4bbf.tar.gz ipecamera-e1265fa32837f457ee2c2fa259d12c9545af4bbf.tar.bz2 ipecamera-e1265fa32837f457ee2c2fa259d12c9545af4bbf.tar.xz ipecamera-e1265fa32837f457ee2c2fa259d12c9545af4bbf.zip | |
First stand-alone ipecamera implementation
Diffstat (limited to 'dma')
| -rw-r--r-- | dma/CMakeLists.txt | 9 | ||||
| -rw-r--r-- | dma/ipe.c | 541 | ||||
| -rw-r--r-- | dma/ipe.h | 42 | ||||
| -rw-r--r-- | dma/ipe_private.h | 59 | ||||
| -rw-r--r-- | dma/ipe_registers.h | 44 | ||||
| -rw-r--r-- | dma/nwl.c | 139 | ||||
| -rw-r--r-- | dma/nwl.h | 46 | ||||
| -rw-r--r-- | dma/nwl_defines.h | 145 | ||||
| -rw-r--r-- | dma/nwl_engine.c | 318 | ||||
| -rw-r--r-- | dma/nwl_engine.h | 12 | ||||
| -rw-r--r-- | dma/nwl_engine_buffers.h | 412 | ||||
| -rw-r--r-- | dma/nwl_irq.c | 119 | ||||
| -rw-r--r-- | dma/nwl_irq.h | 10 | ||||
| -rw-r--r-- | dma/nwl_loopback.c | 255 | ||||
| -rw-r--r-- | dma/nwl_loopback.h | 7 | ||||
| -rw-r--r-- | dma/nwl_private.h | 67 | ||||
| -rw-r--r-- | dma/nwl_register.c | 77 | ||||
| -rw-r--r-- | dma/nwl_register.h | 97 |
18 files changed, 0 insertions, 2399 deletions
diff --git a/dma/CMakeLists.txt b/dma/CMakeLists.txt deleted file mode 100644 index 44bf18c..0000000 --- a/dma/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -include_directories( - ${CMAKE_SOURCE_DIR} -) - - -set(HEADERS ${HEADERS} nwl.h nwl_private.h nwl_engine.h nwl_irq.h nwl_loopback.h nwl_register.h ipe.h ipe_private.h ipe_registers.h) - -add_library(dma STATIC nwl.c nwl_engine.c nwl_irq.c nwl_loopback.c nwl_register.c ipe.c) - diff --git a/dma/ipe.c b/dma/ipe.c deleted file mode 100644 index 61480d4..0000000 --- a/dma/ipe.c +++ /dev/null @@ -1,541 +0,0 @@ -#define _PCILIB_DMA_IPE_C -#define _BSD_SOURCE - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/time.h> -#include <arpa/inet.h> - -#include "pci.h" -#include "pcilib.h" -#include "error.h" -#include "tools.h" - -#include "ipe.h" -#include "ipe_private.h" -#include "ipe_registers.h" - - -#define WR(addr, value) { *(uint32_t*)(ctx->base_addr + addr) = value; } -#define RD(addr, value) { value = *(uint32_t*)(ctx->base_addr + addr); } - - -pcilib_dma_context_t *dma_ipe_init(pcilib_t *pcilib, pcilib_dma_modification_t type, void *arg) { - int err = 0; - - pcilib_model_description_t *model_info = pcilib_get_model_description(pcilib); - - ipe_dma_t *ctx = malloc(sizeof(ipe_dma_t)); - - if (ctx) { - memset(ctx, 0, sizeof(ipe_dma_t)); - ctx->pcilib = pcilib; -// ctx->mode64 = 1; - - memset(ctx->engine, 0, 2 * sizeof(pcilib_dma_engine_description_t)); - ctx->engine[0].addr = 0; - ctx->engine[0].type = PCILIB_DMA_TYPE_PACKET; - ctx->engine[0].direction = PCILIB_DMA_FROM_DEVICE; - ctx->engine[0].addr_bits = 32; - pcilib_set_dma_engine_description(pcilib, 0, &ctx->engine[0]); - pcilib_set_dma_engine_description(pcilib, 1, NULL); - - pcilib_register_bank_t dma_bank = pcilib_find_bank_by_addr(pcilib, PCILIB_REGISTER_BANK_DMA); - if (dma_bank == PCILIB_REGISTER_BANK_INVALID) { - free(ctx); - pcilib_error("DMA Register Bank could not be found"); - return NULL; - } - - ctx->dma_bank = model_info->banks + dma_bank; - ctx->base_addr = pcilib_resolve_register_address(pcilib, ctx->dma_bank->bar, ctx->dma_bank->read_addr); - - err = pcilib_add_registers(ctx->pcilib, 0, ipe_dma_registers); - if (err) { - free(ctx); - pcilib_error("Error adding DMA registers"); - return NULL; - } - } - - return (pcilib_dma_context_t*)ctx; -} - -void dma_ipe_free(pcilib_dma_context_t *vctx) { - ipe_dma_t *ctx = (ipe_dma_t*)vctx; - - if (ctx) { - dma_ipe_stop(vctx, PCILIB_DMA_ENGINE_ALL, PCILIB_DMA_FLAGS_DEFAULT); - free(ctx); - } -} - - -int dma_ipe_start(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags) { - size_t i; - - ipe_dma_t *ctx = (ipe_dma_t*)vctx; - - int preserve = 0; - pcilib_kmem_flags_t kflags; - pcilib_kmem_reuse_state_t reuse_desc, reuse_pages; - - volatile void *desc_va; - volatile uint32_t *last_written_addr_ptr; - - pcilib_register_value_t value; - - uint32_t address64; - - - if (dma == PCILIB_DMA_ENGINE_INVALID) return 0; - else if (dma > 1) return PCILIB_ERROR_INVALID_BANK; - - if (!ctx->started) ctx->started = 1; - - if (flags&PCILIB_DMA_FLAG_PERSISTENT) ctx->preserve = 1; - - if (ctx->pages) return 0; - - kflags = PCILIB_KMEM_FLAG_REUSE|PCILIB_KMEM_FLAG_EXCLUSIVE|PCILIB_KMEM_FLAG_HARDWARE|(ctx->preserve?PCILIB_KMEM_FLAG_PERSISTENT:0); - pcilib_kmem_handle_t *desc = pcilib_alloc_kernel_memory(ctx->pcilib, PCILIB_KMEM_TYPE_CONSISTENT, 1, IPEDMA_DESCRIPTOR_SIZE, IPEDMA_DESCRIPTOR_ALIGNMENT, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_RING, 0x00), kflags); - pcilib_kmem_handle_t *pages = pcilib_alloc_kernel_memory(ctx->pcilib, PCILIB_KMEM_TYPE_DMA_C2S_PAGE, IPEDMA_DMA_PAGES, 0, 0, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_PAGES, 0x00), kflags); - - if (!desc||!pages) { - if (pages) pcilib_free_kernel_memory(ctx->pcilib, pages, 0); - if (desc) pcilib_free_kernel_memory(ctx->pcilib, desc, 0); - return PCILIB_ERROR_MEMORY; - } - reuse_desc = pcilib_kmem_is_reused(ctx->pcilib, desc); - reuse_pages = pcilib_kmem_is_reused(ctx->pcilib, pages); - - if (reuse_desc == reuse_pages) { - if (reuse_desc & PCILIB_KMEM_REUSE_PARTIAL) pcilib_warning("Inconsistent DMA buffers are found (only part of required buffers is available), reinitializing..."); - else if (reuse_desc & PCILIB_KMEM_REUSE_REUSED) { - if ((reuse_desc & PCILIB_KMEM_REUSE_PERSISTENT) == 0) pcilib_warning("Lost DMA buffers are found (non-persistent mode), reinitializing..."); - else if ((reuse_desc & PCILIB_KMEM_REUSE_HARDWARE) == 0) pcilib_warning("Lost DMA buffers are found (missing HW reference), reinitializing..."); - else { -#ifndef IPEDMA_BUG_DMARD - RD(IPEDMA_REG_PAGE_COUNT, value); - - if (value != IPEDMA_DMA_PAGES) pcilib_warning("Inconsistent DMA buffers are found (Number of allocated buffers (%lu) does not match current request (%lu)), reinitializing...", value + 1, IPEDMA_DMA_PAGES); - else -#endif /* IPEDMA_BUG_DMARD */ - preserve = 1; - } - } - } else pcilib_warning("Inconsistent DMA buffers (modes of ring and page buffers does not match), reinitializing...."); - - desc_va = pcilib_kmem_get_ua(ctx->pcilib, desc); - if (ctx->mode64) last_written_addr_ptr = desc_va + 3 * sizeof(uint32_t); - else last_written_addr_ptr = desc_va + 4 * sizeof(uint32_t); - - if (preserve) { - ctx->reused = 1; - ctx->preserve = 1; - - -// usleep(100000); - - // Detect the current state of DMA engine -#ifdef IPEDMA_BUG_DMARD - FILE *f = fopen("/tmp/pcitool_lastread", "r"); - if (!f) pcilib_error("Can't read current status"); - fread(&value, 1, sizeof(pcilib_register_value_t), f); - fclose(f); -#else /* IPEDMA_BUG_DMARD */ - RD(IPEDMA_REG_LAST_READ, value); - // Numbered from 1 in FPGA - value--; -#endif /* IPEDMA_BUG_DMARD */ - - ctx->last_read = value; - } else { - ctx->reused = 0; - - // Disable DMA - WR(IPEDMA_REG_CONTROL, 0x0); - usleep(100000); - - // Reset DMA engine - WR(IPEDMA_REG_RESET, 0x1); - usleep(100000); - WR(IPEDMA_REG_RESET, 0x0); - usleep(100000); - -#ifndef IPEDMA_BUG_DMARD - // Verify PCIe link status - RD(IPEDMA_REG_RESET, value); - if (value != 0x14031700) pcilib_warning("PCIe is not ready, code is %lx", value); -#endif /* IPEDMA_BUG_DMARD */ - - // Enable 64 bit addressing and configure TLP and PACKET sizes (40 bit mode can be used with big pre-allocated buffers later) - if (ctx->mode64) address64 = 0x8000 | (0<<24); - else address64 = 0; - - WR(IPEDMA_REG_TLP_SIZE, address64 | IPEDMA_TLP_SIZE); - WR(IPEDMA_REG_TLP_COUNT, IPEDMA_PAGE_SIZE / (4 * IPEDMA_TLP_SIZE * IPEDMA_CORES)); - - // Setting progress register threshold - WR(IPEDMA_REG_UPDATE_THRESHOLD, IPEDMA_DMA_PROGRESS_THRESHOLD); - - // Reseting configured DMA pages - WR(IPEDMA_REG_PAGE_COUNT, 0); - - // Setting current read position and configuring progress register - WR(IPEDMA_REG_LAST_READ, IPEDMA_DMA_PAGES); - WR(IPEDMA_REG_UPDATE_ADDR, pcilib_kmem_get_block_ba(ctx->pcilib, desc, 0)); - - // Instructing DMA engine that writting should start from the first DMA page - *last_written_addr_ptr = 0;//htonl(pcilib_kmem_get_block_ba(ctx->pcilib, pages, IPEDMA_DMA_PAGES - 1)); - - - for (i = 0; i < IPEDMA_DMA_PAGES; i++) { - uintptr_t bus_addr_check, bus_addr = pcilib_kmem_get_block_ba(ctx->pcilib, pages, i); - WR(IPEDMA_REG_PAGE_ADDR, bus_addr); - if (bus_addr%4096) printf("Bad address %lu: %lx\n", i, bus_addr); - - RD(IPEDMA_REG_PAGE_ADDR, bus_addr_check); - if (bus_addr_check != bus_addr) { - pcilib_error("Written (%x) and read (%x) bus addresses does not match\n", bus_addr, bus_addr_check); - } - - usleep(1000); - } - - // Enable DMA - WR(IPEDMA_REG_CONTROL, 0x1); - - ctx->last_read = IPEDMA_DMA_PAGES - 1; - -#ifdef IPEDMA_BUG_DMARD - FILE *f = fopen("/tmp/pcitool_lastread", "w"); - if (!f) pcilib_error("Can't write current status"); - value = ctx->last_read; - fwrite(&value, 1, sizeof(pcilib_register_value_t), f); - fclose(f); -#endif /* IPEDMA_BUG_DMARD */ - } - -// ctx->last_read_addr = htonl(pcilib_kmem_get_block_ba(ctx->pcilib, pages, ctx->last_read)); - ctx->last_read_addr = pcilib_kmem_get_block_ba(ctx->pcilib, pages, ctx->last_read); - - - ctx->desc = desc; - ctx->pages = pages; - ctx->page_size = pcilib_kmem_get_block_size(ctx->pcilib, pages, 0);; - ctx->ring_size = IPEDMA_DMA_PAGES; - - return 0; -} - -int dma_ipe_stop(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags) { - pcilib_kmem_flags_t kflags; - - ipe_dma_t *ctx = (ipe_dma_t*)vctx; - - if (!ctx->started) return 0; - - if ((dma != PCILIB_DMA_ENGINE_INVALID)&&(dma > 1)) return PCILIB_ERROR_INVALID_BANK; - - // ignoring previous setting if flag specified - if (flags&PCILIB_DMA_FLAG_PERSISTENT) { - ctx->preserve = 0; - } - - if (ctx->preserve) { - kflags = PCILIB_KMEM_FLAG_REUSE; - } else { - kflags = PCILIB_KMEM_FLAG_HARDWARE|PCILIB_KMEM_FLAG_PERSISTENT; - - ctx->started = 0; - - // Disable DMA - WR(IPEDMA_REG_CONTROL, 0); - usleep(100000); - - // Reset DMA engine - WR(IPEDMA_REG_RESET, 0x1); - usleep(100000); - WR(IPEDMA_REG_RESET, 0x0); - usleep(100000); - - // Reseting configured DMA pages - WR(IPEDMA_REG_PAGE_COUNT, 0); - usleep(100000); - } - - // Clean buffers - if (ctx->desc) { - pcilib_free_kernel_memory(ctx->pcilib, ctx->desc, kflags); - ctx->desc = NULL; - } - - if (ctx->pages) { - pcilib_free_kernel_memory(ctx->pcilib, ctx->pages, kflags); - ctx->pages = NULL; - } - - return 0; -} - - -int dma_ipe_get_status(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers) { - size_t i; - ipe_dma_t *ctx = (ipe_dma_t*)vctx; - - void *desc_va = (void*)pcilib_kmem_get_ua(ctx->pcilib, ctx->desc); - uint32_t *last_written_addr_ptr; - uint32_t last_written_addr; - - if (!status) return -1; - - if (ctx->mode64) last_written_addr_ptr = desc_va + 3 * sizeof(uint32_t); - else last_written_addr_ptr = desc_va + 4 * sizeof(uint32_t); - - last_written_addr = *last_written_addr_ptr; - - status->started = ctx->started; - status->ring_size = ctx->ring_size; - status->buffer_size = ctx->page_size; - - // For simplicity, we keep last_read here, and fix in the end - status->ring_tail = ctx->last_read; - - // Find where the ring head is actually are - for (i = 0; i < ctx->ring_size; i++) { - uintptr_t bus_addr = pcilib_kmem_get_block_ba(ctx->pcilib, ctx->pages, i); - - if (bus_addr == last_written_addr) { - status->ring_head = i; - break; - } - } - - if (i == ctx->ring_size) { - if (last_written_addr) { - pcilib_warning("DMA is in unknown state, last_written_addr does not correspond any of available buffers"); - return -1; - } - status->ring_head = 0; - status->ring_tail = 0; - } - - if (n_buffers > ctx->ring_size) n_buffers = ctx->ring_size; - - if (buffers) { - memset(buffers, 0, n_buffers * sizeof(pcilib_dma_buffer_status_t)); - if (status->ring_head >= status->ring_tail) { - for (i = status->ring_tail + 1; (i <= status->ring_head)&&(i < n_buffers); i++) { - buffers[i].used = 1; - buffers[i].size = ctx->page_size; - buffers[i].first = 1; - buffers[i].last = 1; - } - } else { - for (i = 0; (i <= status->ring_head)&&(i < n_buffers); i++) { - buffers[i].used = 1; - buffers[i].size = ctx->page_size; - buffers[i].first = 1; - buffers[i].last = 1; - } - - for (i = status->ring_tail + 1; (i < status->ring_size)&&(i < n_buffers); i++) { - buffers[i].used = 1; - buffers[i].size = ctx->page_size; - buffers[i].first = 1; - buffers[i].last = 1; - } - } - } - - // We actually keep last_read in the ring_tail, so need to increase - if (status->ring_tail != status->ring_head) { - status->ring_tail++; - if (status->ring_tail == status->ring_size) status->ring_tail = 0; - } - - return 0; -} - -int dma_ipe_stream_read(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, pcilib_dma_callback_t cb, void *cbattr) { - int err, ret = PCILIB_STREAMING_REQ_PACKET; - - - pcilib_timeout_t wait = 0; - struct timeval start, cur; - - volatile void *desc_va; - volatile uint32_t *last_written_addr_ptr; - volatile uint32_t *empty_detected_ptr; - - pcilib_dma_flags_t packet_flags = PCILIB_DMA_FLAG_EOP; - -#ifdef IPEDMA_BUG_DMARD - pcilib_register_value_t value; -#endif /* IPEDMA_BUG_DMARD */ - - size_t cur_read; - - ipe_dma_t *ctx = (ipe_dma_t*)vctx; - - err = dma_ipe_start(vctx, dma, PCILIB_DMA_FLAGS_DEFAULT); - if (err) return err; - - desc_va = (void*)pcilib_kmem_get_ua(ctx->pcilib, ctx->desc); - - if (ctx->mode64) last_written_addr_ptr = desc_va + 3 * sizeof(uint32_t); - else last_written_addr_ptr = desc_va + 4 * sizeof(uint32_t); - - empty_detected_ptr = last_written_addr_ptr - 2; - - do { - switch (ret&PCILIB_STREAMING_TIMEOUT_MASK) { - case PCILIB_STREAMING_CONTINUE: - // Hardware indicates that there is no more data pending and we can safely stop if there is no data in the kernel buffers already -#ifdef IPEDMA_SUPPORT_EMPTY_DETECTED - if (*empty_detected_ptr) - wait = 0; - else -#endif /* IPEDMA_SUPPORT_EMPTY_DETECTED */ - wait = IPEDMA_DMA_TIMEOUT; - break; - case PCILIB_STREAMING_WAIT: - wait = (timeout > IPEDMA_DMA_TIMEOUT)?timeout:IPEDMA_DMA_TIMEOUT; - break; -// case PCILIB_STREAMING_CHECK: wait = 0; break; - } - -#ifdef IPEDMA_DEBUG - printf("Waiting for data: %u (last read) 0x%x (last read addr) 0x%x (last_written)\n", ctx->last_read, ctx->last_read_addr, *last_written_addr_ptr); -#endif /* IPEDMA_DEBUG */ - - gettimeofday(&start, NULL); - memcpy(&cur, &start, sizeof(struct timeval)); - while (((*last_written_addr_ptr == 0)||(ctx->last_read_addr == (*last_written_addr_ptr)))&&((wait == PCILIB_TIMEOUT_INFINITE)||(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < wait))) { - usleep(10); -#ifdef IPEDMA_SUPPORT_EMPTY_DETECTED - if ((ret != PCILIB_STREAMING_REQ_PACKET)&&(*empty_detected_ptr)) break; -#endif /* IPEDMA_SUPPORT_EMPTY_DETECTED */ - gettimeofday(&cur, NULL); - } - - // Failing out if we exited on timeout - if ((ctx->last_read_addr == (*last_written_addr_ptr))||(*last_written_addr_ptr == 0)) { -#ifdef IPEDMA_SUPPORT_EMPTY_DETECTED -# ifdef IPEDMA_DEBUG - if ((wait)&&(*last_written_addr_ptr)&&(!*empty_detected_ptr)) - pcilib_warning("The empty_detected flag is not set, but no data arrived within %lu us\n", wait); -# endif /* IPEDMA_DEBUG */ -#endif /* IPEDMA_SUPPORT_EMPTY_DETECTED */ - return (ret&PCILIB_STREAMING_FAIL)?PCILIB_ERROR_TIMEOUT:0; - } - - // Getting next page to read - cur_read = ctx->last_read + 1; - if (cur_read == ctx->ring_size) cur_read = 0; - -#ifdef IPEDMA_DEBUG - printf("Reading: %u (last read) 0x%x (last read addr) 0x%x (last_written)\n", cur_read, ctx->last_read_addr, *last_written_addr_ptr); -#endif /* IPEDMA_DEBUG */ - -#ifdef IPEDMA_DETECT_PACKETS - if ((*empty_detected_ptr)&&(pcilib_kmem_get_block_ba(ctx->pcilib, ctx->pages, cur_read) == (*last_written_addr_ptr))) packet_flags = PCILIB_DMA_FLAG_EOP; - else packet_flags = 0; -#endif /* IPEDMA_DETECT_PACKETS */ - - pcilib_kmem_sync_block(ctx->pcilib, ctx->pages, PCILIB_KMEM_SYNC_FROMDEVICE, cur_read); - void *buf = pcilib_kmem_get_block_ua(ctx->pcilib, ctx->pages, cur_read); - ret = cb(cbattr, packet_flags, ctx->page_size, buf); - if (ret < 0) return -ret; - -// DS: Fixme, it looks like we can avoid calling this for the sake of performance -// pcilib_kmem_sync_block(ctx->pcilib, ctx->pages, PCILIB_KMEM_SYNC_TODEVICE, cur_read); - - // Numbered from 1 - WR(IPEDMA_REG_LAST_READ, cur_read + 1); - - ctx->last_read = cur_read; -// ctx->last_read_addr = htonl(pcilib_kmem_get_block_ba(ctx->pcilib, ctx->pages, cur_read)); - ctx->last_read_addr = pcilib_kmem_get_block_ba(ctx->pcilib, ctx->pages, cur_read); - -#ifdef IPEDMA_BUG_DMARD - FILE *f = fopen("/tmp/pcitool_lastread", "w"); - if (!f) pcilib_error("Can't write current status"); - value = cur_read; - fwrite(&value, 1, sizeof(pcilib_register_value_t), f); - fclose(f); -#endif /* IPEDMA_BUG_DMARD */ - - } while (ret); - - return 0; -} - -double dma_ipe_benchmark(pcilib_dma_context_t *vctx, pcilib_dma_engine_addr_t dma, uintptr_t addr, size_t size, size_t iterations, pcilib_dma_direction_t direction) { - int err = 0; - - ipe_dma_t *ctx = (ipe_dma_t*)vctx; - - int iter; - size_t us = 0; - struct timeval start, cur; - - void *buf; - size_t bytes, rbytes; - - if ((direction == PCILIB_DMA_TO_DEVICE)||(direction == PCILIB_DMA_BIDIRECTIONAL)) return -1.; - - if ((dma != PCILIB_DMA_ENGINE_INVALID)&&(dma > 1)) return -1.; - - err = dma_ipe_start(vctx, 0, PCILIB_DMA_FLAGS_DEFAULT); - if (err) return err; - - WR(IPEDMA_REG_CONTROL, 0x0); - - err = pcilib_skip_dma(ctx->pcilib, 0); - if (err) { - pcilib_error("Can't start benchmark, devices continuously writes unexpected data using DMA engine"); - return -1; - } - - if (size%IPEDMA_PAGE_SIZE) size = (1 + size / IPEDMA_PAGE_SIZE) * IPEDMA_PAGE_SIZE; - - // Allocate memory and prepare data - buf = malloc(size); - if (!buf) return -1; - - for (iter = 0; iter < iterations; iter++) { - gettimeofday(&start, NULL); - - // Starting DMA - WR(IPEDMA_REG_CONTROL, 0x1); - - for (bytes = 0; bytes < size; bytes += rbytes) { - err = pcilib_read_dma(ctx->pcilib, 0, addr, size - bytes, buf + bytes, &rbytes); - if (err) { - pcilib_error("Can't read data from DMA, error %i", err); - return -1; - } - } - - // Stopping DMA - WR(IPEDMA_REG_CONTROL, 0x0); - if (err) break; - - gettimeofday(&cur, NULL); - us += ((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)); - - err = pcilib_skip_dma(ctx->pcilib, 0); - if (err) { - pcilib_error("Can't start iteration, devices continuously writes unexpected data using DMA engine"); - break; - } - } - - free(buf); - - return err?-1:((1. * size * iterations * 1000000) / (1024. * 1024. * us)); -} diff --git a/dma/ipe.h b/dma/ipe.h deleted file mode 100644 index 2c34ff1..0000000 --- a/dma/ipe.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _PCILIB_DMA_IPE_H -#define _PCILIB_DMA_IPE_H - -#include <stdio.h> -#include "../pcilib.h" - -//#define PCILIB_NWL_MODIFICATION_IPECAMERA 0x100 - -pcilib_dma_context_t *dma_ipe_init(pcilib_t *ctx, pcilib_dma_modification_t type, void *arg); -void dma_ipe_free(pcilib_dma_context_t *vctx); - -int dma_ipe_get_status(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers); - - -int dma_ipe_start(pcilib_dma_context_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags); -int dma_ipe_stop(pcilib_dma_context_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags); - -int dma_ipe_stream_read(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, pcilib_dma_callback_t cb, void *cbattr); -double dma_ipe_benchmark(pcilib_dma_context_t *vctx, pcilib_dma_engine_addr_t dma, uintptr_t addr, size_t size, size_t iterations, pcilib_dma_direction_t direction); - - -#ifdef _PCILIB_DMA_IPE_C -pcilib_dma_api_description_t ipe_dma_api = { - "ipe_dma", - dma_ipe_init, - dma_ipe_free, - dma_ipe_get_status, - NULL, - NULL, - NULL, - dma_ipe_start, - dma_ipe_stop, - NULL, - dma_ipe_stream_read, - dma_ipe_benchmark -}; -#else -extern pcilib_dma_api_description_t ipe_dma_api; -#endif - - -#endif /* _PCILIB_DMA_IPE_H */ diff --git a/dma/ipe_private.h b/dma/ipe_private.h deleted file mode 100644 index fd44011..0000000 --- a/dma/ipe_private.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef _PCILIB_DMA_IPE_PRIVATE_H -#define _PCILIB_DMA_IPE_PRIVATE_H - -#define IPEDMA_CORES 1 -#define IPEDMA_TLP_SIZE 32 -#define IPEDMA_PAGE_SIZE 4096 -#define IPEDMA_DMA_PAGES 16 /**< number of DMA pages in the ring buffer to allocate */ -#define IPEDMA_DMA_PROGRESS_THRESHOLD 1 /**< how many pages the DMA engine should fill before reporting progress */ -#define IPEDMA_DESCRIPTOR_SIZE 128 -#define IPEDMA_DESCRIPTOR_ALIGNMENT 64 - -//#define IPEDMA_DEBUG -//#define IPEDMA_BUG_DMARD /**< No register read during DMA transfer */ -//#define IPEDMA_DETECT_PACKETS /**< Using empty_deceted flag */ -#define IPEDMA_SUPPORT_EMPTY_DETECTED /**< Avoid waiting for data when empty_detected flag is set in hardware */ -#define IPEDMA_DMA_TIMEOUT 100000 /**< us, overrides PCILIB_DMA_TIMEOUT (actual hardware timeout is 50ms according to Lorenzo) */ - -#define IPEDMA_REG_RESET 0x00 -#define IPEDMA_REG_CONTROL 0x04 -#define IPEDMA_REG_TLP_SIZE 0x0C -#define IPEDMA_REG_TLP_COUNT 0x10 -#define IPEDMA_REG_PAGE_ADDR 0x50 -#define IPEDMA_REG_UPDATE_ADDR 0x54 -#define IPEDMA_REG_LAST_READ 0x58 -#define IPEDMA_REG_PAGE_COUNT 0x5C -#define IPEDMA_REG_UPDATE_THRESHOLD 0x60 - - - -typedef struct ipe_dma_s ipe_dma_t; - -struct ipe_dma_s { - struct pcilib_dma_context_s dmactx; - pcilib_dma_engine_description_t engine[2]; - - pcilib_t *pcilib; - - pcilib_register_bank_description_t *dma_bank; - char *base_addr; - - pcilib_irq_type_t irq_enabled; /**< indicates that IRQs are enabled */ - pcilib_irq_type_t irq_preserve; /**< indicates that IRQs should not be disabled during clean-up */ - int irq_started; /**< indicates that IRQ subsystem is initialized (detecting which types should be preserverd) */ - - int started; /**< indicates that DMA buffers are initialized and reading is allowed */ - int writting; /**< indicates that we are in middle of writting packet */ - int reused; /**< indicates that DMA was found intialized, buffers were reused, and no additional initialization is needed */ - int preserve; /**< indicates that DMA should not be stopped during clean-up */ - int mode64; /**< indicates 64-bit operation mode */ - - pcilib_kmem_handle_t *desc; /**< in-memory status descriptor written by DMA engine upon operation progess */ - pcilib_kmem_handle_t *pages; /**< collection of memory-locked pages for DMA operation */ - - size_t ring_size, page_size; - size_t last_read, last_read_addr, last_written; - -}; - -#endif /* _PCILIB_DMA_IPE_PRIVATE_H */ diff --git a/dma/ipe_registers.h b/dma/ipe_registers.h deleted file mode 100644 index 17fc41a..0000000 --- a/dma/ipe_registers.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef _PCILIB_DMA_IPE_REGISTERS_H -#define _PCILIB_DMA_IPE_REGISTERS_H - -#ifdef _PCILIB_DMA_IPE_C -static pcilib_register_description_t ipe_dma_registers[] = { - {0x0000, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dcr", "Device Control Status Register"}, - {0x0000, 0, 1, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "reset_dma", ""}, - {0x0000, 16, 4, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "datapath_width", ""}, - {0x0000, 24, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "fpga_family", ""}, - {0x0004, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "ddmacr", "Device DMA Control Status Register"}, - {0x0004, 0, 1, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_start", "Start writting memory"}, - {0x0004, 5, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_relxed_order", ""}, - {0x0004, 6, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_nosnoop", ""}, - {0x0004, 7, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_int_dis", ""}, - {0x0004, 16, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_start", ""}, - {0x0004, 21, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_relaxed_order", ""}, - {0x0004, 22, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_nosnoop", ""}, - {0x0004, 23, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mrd_int_dis", ""}, - {0x000C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_size", "DMA TLP size"}, - {0x000C, 0, 16, 0x20, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_len", "Max TLP size"}, - {0x000C, 16, 3, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_tlp_tc", "TC for TLP packets"}, - {0x000C, 19, 1, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_64b_en", "Enable 64 bit memory addressing"}, - {0x000C, 20, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_phant_func_dis", "Disable MWR phantom function"}, - {0x000C, 24, 8, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_up_addr", "Upper address for 64 bit memory addressing"}, - {0x0010, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_count", "Write DMA TLP Count"}, - {0x0014, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_pattern", "DMA generator data pattern"}, - {0x0028, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_perf", "MWR Performance"}, - {0x003C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_lnk_width", "Negotiated and max width of PCIe Link"}, - {0x003C, 0, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_lnk_width", "Max link width"}, - {0x003C, 8, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_prg_max_lnk_width", "Negotiated link width"}, - {0x0040, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_payload_size", ""}, - {0x0040, 0, 4, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_payload_size", "Max payload size"}, - {0x0040, 8, 3, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_prg_max_payload_size", "Prog max payload size"}, - {0x0040, 16, 3, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_max_rd_req_size", "Max read request size"}, - {0x0050, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "desc_mem_din", "Descriptor memory"}, - {0x0054, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "update_addr", "Address of progress register"}, - {0x0058, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "last_descriptor_read", "Last descriptor read by the host"}, - {0x005C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "desc_mem_addr", "Number of descriptors configured"}, - {0x0060, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "update_thresh", "Update threshold of progress register"}, - {0, 0, 0, 0, 0x00000000, 0, 0, 0, NULL, NULL} -}; -#endif /* _PCILIB_DMA_IPE_C */ - -#endif /* _PCILIB_DMA_IPE_REGISTERS_H */ diff --git a/dma/nwl.c b/dma/nwl.c deleted file mode 100644 index 52b46ef..0000000 --- a/dma/nwl.c +++ /dev/null @@ -1,139 +0,0 @@ -#define _PCILIB_DMA_NWL_C -#define _BSD_SOURCE - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/time.h> - -#include "pci.h" -#include "pcilib.h" -#include "error.h" -#include "tools.h" -#include "nwl_private.h" - -#include "nwl_defines.h" - -int dma_nwl_start(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags) { - int err; - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - if (!ctx->started) { - // global initialization, should we do anything? - ctx->started = 1; - } - - if (dma == PCILIB_DMA_ENGINE_INVALID) return 0; - else if (dma > ctx->n_engines) return PCILIB_ERROR_INVALID_BANK; - - if (flags&PCILIB_DMA_FLAG_PERSISTENT) ctx->engines[dma].preserve = 1; - - err = dma_nwl_start_engine(ctx, dma); - - return err; -} - -int dma_nwl_stop(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags) { - int err; - int preserving = 0; - - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - if (!ctx->started) return 0; - - // stop everything - if (dma == PCILIB_DMA_ENGINE_INVALID) { - for (dma = 0; dma < ctx->n_engines; dma++) { - if (flags&PCILIB_DMA_FLAG_PERSISTENT) { - ctx->engines[dma].preserve = 0; - } - - if (ctx->engines[dma].preserve) preserving = 1; - - err = dma_nwl_stop_engine(ctx, dma); - if (err) return err; - } - - // global cleanup, should we do anything? - if (!preserving) { - ctx->started = 0; - } - - return 0; - } - - if (dma > ctx->n_engines) return PCILIB_ERROR_INVALID_BANK; - - // ignorign previous setting if flag specified - if (flags&PCILIB_DMA_FLAG_PERSISTENT) { - ctx->engines[dma].preserve = 0; - } - - return dma_nwl_stop_engine(ctx, dma); -} - - -pcilib_dma_context_t *dma_nwl_init(pcilib_t *pcilib, pcilib_dma_modification_t type, void *arg) { - int i; - int err; - pcilib_dma_engine_t n_engines; - - pcilib_model_description_t *model_info = pcilib_get_model_description(pcilib); - - nwl_dma_t *ctx = malloc(sizeof(nwl_dma_t)); - if (ctx) { - memset(ctx, 0, sizeof(nwl_dma_t)); - ctx->pcilib = pcilib; - ctx->type = type; - - if (type == PCILIB_NWL_MODIFICATION_IPECAMERA) { - ctx->dmactx.ignore_eop = 1; - } - - pcilib_register_bank_t dma_bank = pcilib_find_bank_by_addr(pcilib, PCILIB_REGISTER_BANK_DMA); - if (dma_bank == PCILIB_REGISTER_BANK_INVALID) { - free(ctx); - pcilib_error("DMA Register Bank could not be found"); - return NULL; - } - - ctx->dma_bank = model_info->banks + dma_bank; - ctx->base_addr = pcilib_resolve_register_address(pcilib, ctx->dma_bank->bar, ctx->dma_bank->read_addr); - - for (i = 0, n_engines = 0; i < 2 * PCILIB_MAX_DMA_ENGINES; i++) { - char *addr = ctx->base_addr + DMA_OFFSET + i * DMA_ENGINE_PER_SIZE; - - memset(ctx->engines + n_engines, 0, sizeof(pcilib_nwl_engine_description_t)); - - err = dma_nwl_read_engine_config(ctx, ctx->engines + n_engines, addr); - if (err) continue; - - pcilib_set_dma_engine_description(pcilib, n_engines, (pcilib_dma_engine_description_t*)(ctx->engines + n_engines)); - ++n_engines; - } - pcilib_set_dma_engine_description(pcilib, n_engines, NULL); - - ctx->n_engines = n_engines; - - err = nwl_add_registers(ctx); - if (err) { - free(ctx); - pcilib_error("Failed to add DMA registers"); - return NULL; - } - } - return (pcilib_dma_context_t*)ctx; -} - -void dma_nwl_free(pcilib_dma_context_t *vctx) { - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - if (ctx) { - if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) dma_nwl_stop_loopback(ctx); - dma_nwl_free_irq(ctx); - dma_nwl_stop(vctx, PCILIB_DMA_ENGINE_ALL, PCILIB_DMA_FLAGS_DEFAULT); - - free(ctx); - } -} diff --git a/dma/nwl.h b/dma/nwl.h deleted file mode 100644 index 21df94c..0000000 --- a/dma/nwl.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef _PCILIB_DMA_NWL_H -#define _PCILIB_DMA_NWL_H - -#include <stdio.h> -#include "../pcilib.h" - -#define PCILIB_NWL_MODIFICATION_IPECAMERA 0x100 - -pcilib_dma_context_t *dma_nwl_init(pcilib_t *ctx, pcilib_dma_modification_t type, void *arg); -void dma_nwl_free(pcilib_dma_context_t *vctx); - -int dma_nwl_get_status(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers); - -int dma_nwl_enable_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t type, pcilib_dma_flags_t flags); -int dma_nwl_disable_irq(pcilib_dma_context_t *vctx, pcilib_dma_flags_t flags); -int dma_nwl_acknowledge_irq(pcilib_dma_context_t *ctx, pcilib_irq_type_t irq_type, pcilib_irq_source_t irq_source); - -int dma_nwl_start(pcilib_dma_context_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags); -int dma_nwl_stop(pcilib_dma_context_t *ctx, pcilib_dma_engine_t dma, pcilib_dma_flags_t flags); - -int dma_nwl_write_fragment(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, void *data, size_t *written); -int dma_nwl_stream_read(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, pcilib_dma_callback_t cb, void *cbattr); -double dma_nwl_benchmark(pcilib_dma_context_t *vctx, pcilib_dma_engine_addr_t dma, uintptr_t addr, size_t size, size_t iterations, pcilib_dma_direction_t direction); - - -#ifdef _PCILIB_DMA_NWL_C -pcilib_dma_api_description_t nwl_dma_api = { - "nwl_dma", - dma_nwl_init, - dma_nwl_free, - dma_nwl_get_status, - dma_nwl_enable_irq, - dma_nwl_disable_irq, - dma_nwl_acknowledge_irq, - dma_nwl_start, - dma_nwl_stop, - dma_nwl_write_fragment, - dma_nwl_stream_read, - dma_nwl_benchmark -}; -#else -extern pcilib_dma_api_description_t nwl_dma_api; -#endif - - -#endif /* _PCILIB_DMA_NWL_H */ diff --git a/dma/nwl_defines.h b/dma/nwl_defines.h deleted file mode 100644 index ce3b686..0000000 --- a/dma/nwl_defines.h +++ /dev/null @@ -1,145 +0,0 @@ -/** @name Buffer Descriptor offsets - * USR fields are defined by higher level IP. For example, checksum offload - * setup for EMAC type devices. The 1st 8 words are utilized by hardware. Any - * words after the 8th are for software use only. - * @{ - */ -#define DMA_BD_BUFL_STATUS_OFFSET 0x00 /**< Buffer length + status */ -#define DMA_BD_USRL_OFFSET 0x04 /**< User logic specific - LSBytes */ -#define DMA_BD_USRH_OFFSET 0x08 /**< User logic specific - MSBytes */ -#define DMA_BD_CARDA_OFFSET 0x0C /**< Card address */ -#define DMA_BD_BUFL_CTRL_OFFSET 0x10 /**< Buffer length + control */ -#define DMA_BD_BUFAL_OFFSET 0x14 /**< Buffer address LSBytes */ -#define DMA_BD_BUFAH_OFFSET 0x18 /**< Buffer address MSBytes */ -#define DMA_BD_NDESC_OFFSET 0x1C /**< Next descriptor pointer */ - -/* Bit masks for some BD fields */ -#define DMA_BD_BUFL_MASK 0x000FFFFF /**< Byte count */ -#define DMA_BD_STATUS_MASK 0xFF000000 /**< Status Flags */ -#define DMA_BD_CTRL_MASK 0xFF000000 /**< Control Flags */ - -/* Bit masks for BD control field */ -#define DMA_BD_INT_ERROR_MASK 0x02000000 /**< Intr on error */ -#define DMA_BD_INT_COMP_MASK 0x01000000 /**< Intr on BD completion */ - -/* Bit masks for BD status field */ -#define DMA_BD_SOP_MASK 0x80000000 /**< Start of packet */ -#define DMA_BD_EOP_MASK 0x40000000 /**< End of packet */ -#define DMA_BD_ERROR_MASK 0x10000000 /**< BD had error */ -#define DMA_BD_USER_HIGH_ZERO_MASK 0x08000000 /**< User High Status zero */ -#define DMA_BD_USER_LOW_ZERO_MASK 0x04000000 /**< User Low Status zero */ -#define DMA_BD_SHORT_MASK 0x02000000 /**< BD not fully used */ -#define DMA_BD_COMP_MASK 0x01000000 /**< BD completed */ - - - -#define DMA_BD_MINIMUM_ALIGNMENT 0x40 /**< Minimum byte alignment */ - -/* Common DMA registers */ -#define REG_DMA_CTRL_STATUS 0x4000 /**< DMA Common Ctrl & Status */ - -/* These engine registers are applicable to both S2C and C2S channels. - * Register field mask and shift definitions are later in this file. - */ - -#define REG_DMA_ENG_CAP 0x00000000 /**< DMA Engine Capabilities */ -#define REG_DMA_ENG_CTRL_STATUS 0x00000004 /**< DMA Engine Control */ -#define REG_DMA_ENG_NEXT_BD 0x00000008 /**< HW Next desc pointer */ -#define REG_SW_NEXT_BD 0x0000000C /**< SW Next desc pointer */ -#define REG_DMA_ENG_LAST_BD 0x00000010 /**< HW Last completed pointer */ -#define REG_DMA_ENG_ACTIVE_TIME 0x00000014 /**< DMA Engine Active Time */ -#define REG_DMA_ENG_WAIT_TIME 0x00000018 /**< DMA Engine Wait Time */ -#define REG_DMA_ENG_COMP_BYTES 0x0000001C /**< DMA Engine Completed Bytes */ - -/* Register masks. The following constants define bit locations of various - * control bits in the registers. For further information on the meaning of - * the various bit masks, refer to the hardware spec. - * - * Masks have been written assuming HW bits 0-31 correspond to SW bits 0-31 - */ - -/** @name Bitmasks of REG_DMA_CTRL_STATUS register. - * @{ - */ -#define DMA_INT_ENABLE 0x00000001 /**< Enable global interrupts */ -#define DMA_INT_DISABLE 0x00000000 /**< Disable interrupts */ -#define DMA_INT_ACTIVE_MASK 0x00000002 /**< Interrupt active? */ -#define DMA_INT_PENDING_MASK 0x00000004 /**< Engine interrupt pending */ -#define DMA_INT_MSI_MODE 0x00000008 /**< MSI or Legacy mode? */ -#define DMA_USER_INT_ENABLE 0x00000010 /**< Enable user interrupts */ -#define DMA_USER_INT_ACTIVE_MASK 0x00000020 /**< Int - user interrupt */ -#define DMA_USER_INT_ACK 0x00000020 /**< Acknowledge */ -#define DMA_MPS_USED 0x00000700 /**< MPS Used */ -#define DMA_MRRS_USED 0x00007000 /**< MRRS Used */ -#define DMA_S2C_ENG_INT_VAL 0x00FF0000 /**< IRQ value of 1st 8 S2Cs */ -#define DMA_C2S_ENG_INT_VAL 0xFF000000 /**< IRQ value of 1st 8 C2Ss */ - -/** @name Bitmasks of REG_DMA_ENG_CAP register. - * @{ - */ -/* DMA engine characteristics */ -#define DMA_ENG_PRESENT_MASK 0x00000001 /**< DMA engine present? */ -#define DMA_ENG_DIRECTION_MASK 0x00000002 /**< DMA engine direction */ -#define DMA_ENG_C2S 0x00000002 /**< DMA engine - C2S */ -#define DMA_ENG_S2C 0x00000000 /**< DMA engine - S2C */ -#define DMA_ENG_TYPE_MASK 0x00000030 /**< DMA engine type */ -#define DMA_ENG_BLOCK 0x00000000 /**< DMA engine - Block type */ -#define DMA_ENG_PACKET 0x00000010 /**< DMA engine - Packet type */ -#define DMA_ENG_NUMBER 0x0000FF00 /**< DMA engine number */ -#define DMA_ENG_BD_MAX_BC 0x3F000000 /**< DMA engine max buffer size */ - - -/* Shift constants for selected masks */ -#define DMA_ENG_NUMBER_SHIFT 8 -#define DMA_ENG_BD_MAX_BC_SHIFT 24 - -/** @name Bitmasks of REG_DMA_ENG_CTRL_STATUS register. - * @{ - */ -/* Interrupt activity and acknowledgement bits */ -#define DMA_ENG_INT_ENABLE 0x00000001 /**< Enable interrupts */ -#define DMA_ENG_INT_DISABLE 0x00000000 /**< Disable interrupts */ -#define DMA_ENG_INT_ACTIVE_MASK 0x00000002 /**< Interrupt active? */ -#define DMA_ENG_INT_ACK 0x00000002 /**< Interrupt ack */ -#define DMA_ENG_INT_BDCOMP 0x00000004 /**< Int - BD completion */ -#define DMA_ENG_INT_BDCOMP_ACK 0x00000004 /**< Acknowledge */ -#define DMA_ENG_INT_ALERR 0x00000008 /**< Int - BD align error */ -#define DMA_ENG_INT_ALERR_ACK 0x00000008 /**< Acknowledge */ -#define DMA_ENG_INT_FETERR 0x00000010 /**< Int - BD fetch error */ -#define DMA_ENG_INT_FETERR_ACK 0x00000010 /**< Acknowledge */ -#define DMA_ENG_INT_ABORTERR 0x00000020 /**< Int - DMA abort error */ -#define DMA_ENG_INT_ABORTERR_ACK 0x00000020 /**< Acknowledge */ -#define DMA_ENG_INT_CHAINEND 0x00000080 /**< Int - BD chain ended */ -#define DMA_ENG_INT_CHAINEND_ACK 0x00000080 /**< Acknowledge */ - -/* DMA engine control */ -#define DMA_ENG_ENABLE_MASK 0x00000100 /**< DMA enabled? */ -#define DMA_ENG_ENABLE 0x00000100 /**< Enable DMA */ -#define DMA_ENG_DISABLE 0x00000000 /**< Disable DMA */ -#define DMA_ENG_STATE_MASK 0x00000C00 /**< Current DMA state? */ -#define DMA_ENG_RUNNING 0x00000400 /**< DMA running */ -#define DMA_ENG_IDLE 0x00000000 /**< DMA idle */ -#define DMA_ENG_WAITING 0x00000800 /**< DMA waiting */ -#define DMA_ENG_STATE_WAITED 0x00001000 /**< DMA waited earlier */ -#define DMA_ENG_WAITED_ACK 0x00001000 /**< Acknowledge */ -#define DMA_ENG_USER_RESET 0x00004000 /**< Reset only user logic */ -#define DMA_ENG_RESET 0x00008000 /**< Reset DMA engine + user */ - -#define DMA_ENG_ALLINT_MASK 0x000000BE /**< To get only int events */ - -#define DMA_ENGINE_PER_SIZE 0x100 /**< Separation between engine regs */ -#define DMA_OFFSET 0 /**< Starting register offset */ - /**< Size of DMA engine reg space */ -#define DMA_SIZE (MAX_DMA_ENGINES * DMA_ENGINE_PER_SIZE) - - -#define TX_CONFIG_ADDRESS 0x9108 /* Reg for controlling TX data */ -#define RX_CONFIG_ADDRESS 0x9100 /* Reg for controlling RX pkt generator */ -#define PKT_SIZE_ADDRESS 0x9104 /* Reg for programming packet size */ -#define STATUS_ADDRESS 0x910C /* Reg for checking TX pkt checker status */ - -/* Test start / stop conditions */ -#define PKTCHKR 0x00000001 /* Enable TX packet checker */ -#define PKTGENR 0x00000001 /* Enable RX packet generator */ -#define CHKR_MISMATCH 0x00000001 /* TX checker reported data mismatch */ -#define LOOPBACK 0x00000002 /* Enable TX data loopback onto RX */ diff --git a/dma/nwl_engine.c b/dma/nwl_engine.c deleted file mode 100644 index f541d0b..0000000 --- a/dma/nwl_engine.c +++ /dev/null @@ -1,318 +0,0 @@ -#define _BSD_SOURCE - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/time.h> - -#include "pci.h" -#include "pcilib.h" -#include "error.h" -#include "tools.h" -#include "nwl_private.h" - -#include "nwl_defines.h" - -#include "nwl_engine_buffers.h" - -int dma_nwl_read_engine_config(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, char *base) { - uint32_t val; - - info->base_addr = base; - - nwl_read_register(val, ctx, base, REG_DMA_ENG_CAP); - - if ((val & DMA_ENG_PRESENT_MASK) == 0) return PCILIB_ERROR_NOTAVAILABLE; - - info->desc.addr = (val & DMA_ENG_NUMBER) >> DMA_ENG_NUMBER_SHIFT; - if ((info->desc.addr > PCILIB_MAX_DMA_ENGINES)||(info->desc.addr < 0)) return PCILIB_ERROR_INVALID_DATA; - - switch (val & DMA_ENG_DIRECTION_MASK) { - case DMA_ENG_C2S: - info->desc.direction = PCILIB_DMA_FROM_DEVICE; - break; - default: - info->desc.direction = PCILIB_DMA_TO_DEVICE; - } - - switch (val & DMA_ENG_TYPE_MASK) { - case DMA_ENG_BLOCK: - info->desc.type = PCILIB_DMA_TYPE_BLOCK; - break; - case DMA_ENG_PACKET: - info->desc.type = PCILIB_DMA_TYPE_PACKET; - break; - default: - info->desc.type = PCILIB_DMA_TYPE_UNKNOWN; - } - - info->desc.addr_bits = (val & DMA_ENG_BD_MAX_BC) >> DMA_ENG_BD_MAX_BC_SHIFT; - - info->base_addr = base; - - return 0; -} - -int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { - int err; - uint32_t val; - uint32_t ring_pa; - struct timeval start, cur; - - pcilib_nwl_engine_description_t *info = ctx->engines + dma; - char *base = ctx->engines[dma].base_addr; - - if (info->started) return 0; - - - // This will only successed if there are no parallel access to DMA engine - err = dma_nwl_allocate_engine_buffers(ctx, info); - if (err) { - info->started = 1; - dma_nwl_stop_engine(ctx, dma); - return err; - } - - if (info->reused) { - info->preserve = 1; - - dma_nwl_acknowledge_irq((pcilib_dma_context_t*)ctx, PCILIB_DMA_IRQ, dma); - -#ifdef NWL_GENERATE_DMA_IRQ - dma_nwl_enable_engine_irq(ctx, dma); -#endif /* NWL_GENERATE_DMA_IRQ */ - } else { - // Disable IRQs - err = dma_nwl_disable_engine_irq(ctx, dma); - if (err) { - info->started = 1; - dma_nwl_stop_engine(ctx, dma); - return err; - } - - // Disable Engine & Reseting - val = DMA_ENG_DISABLE|DMA_ENG_USER_RESET; - nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - - gettimeofday(&start, NULL); - do { - nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - gettimeofday(&cur, NULL); - } while ((val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT)); - - if (val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET)) { - pcilib_error("Timeout during reset of DMA engine %i", info->desc.addr); - - info->started = 1; - dma_nwl_stop_engine(ctx, dma); - return PCILIB_ERROR_TIMEOUT; - } - - val = DMA_ENG_RESET; - nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - - gettimeofday(&start, NULL); - do { - nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - gettimeofday(&cur, NULL); - } while ((val & DMA_ENG_RESET)&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT)); - - if (val & DMA_ENG_RESET) { - pcilib_error("Timeout during reset of DMA engine %i", info->desc.addr); - - info->started = 1; - dma_nwl_stop_engine(ctx, dma); - return PCILIB_ERROR_TIMEOUT; - } - - dma_nwl_acknowledge_irq((pcilib_dma_context_t*)ctx, PCILIB_DMA_IRQ, dma); - - ring_pa = pcilib_kmem_get_pa(ctx->pcilib, info->ring); - nwl_write_register(ring_pa, ctx, info->base_addr, REG_DMA_ENG_NEXT_BD); - nwl_write_register(ring_pa, ctx, info->base_addr, REG_SW_NEXT_BD); - - __sync_synchronize(); - - nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); - val |= (DMA_ENG_ENABLE); - nwl_write_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); - - __sync_synchronize(); - -#ifdef NWL_GENERATE_DMA_IRQ - dma_nwl_enable_engine_irq(ctx, dma); -#endif /* NWL_GENERATE_DMA_IRQ */ - - if (info->desc.direction == PCILIB_DMA_FROM_DEVICE) { - ring_pa += (info->ring_size - 1) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - nwl_write_register(ring_pa, ctx, info->base_addr, REG_SW_NEXT_BD); - - info->tail = 0; - info->head = (info->ring_size - 1); - } else { - info->tail = 0; - info->head = 0; - } - } - - info->started = 1; - - return 0; -} - - -int dma_nwl_stop_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { - int err; - uint32_t val; - uint32_t ring_pa; - struct timeval start, cur; - pcilib_kmem_flags_t flags; - - - pcilib_nwl_engine_description_t *info = ctx->engines + dma; - char *base = ctx->engines[dma].base_addr; - - if (!info->started) return 0; - - info->started = 0; - - err = dma_nwl_disable_engine_irq(ctx, dma); - if (err) return err; - - if (!info->preserve) { - // Stopping DMA is not enough reset is required - val = DMA_ENG_DISABLE|DMA_ENG_USER_RESET|DMA_ENG_RESET; - nwl_write_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - - gettimeofday(&start, NULL); - do { - nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); - gettimeofday(&cur, NULL); - } while ((val & (DMA_ENG_RUNNING))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT)); - - if (info->ring) { - ring_pa = pcilib_kmem_get_pa(ctx->pcilib, info->ring); - nwl_write_register(ring_pa, ctx, info->base_addr, REG_DMA_ENG_NEXT_BD); - nwl_write_register(ring_pa, ctx, info->base_addr, REG_SW_NEXT_BD); - } - } - - dma_nwl_acknowledge_irq((pcilib_dma_context_t*)ctx, PCILIB_DMA_IRQ, dma); - - if (info->preserve) { - flags = PCILIB_KMEM_FLAG_REUSE; - } else { - flags = PCILIB_KMEM_FLAG_HARDWARE|PCILIB_KMEM_FLAG_PERSISTENT; - } - - // Clean buffers - if (info->ring) { - pcilib_free_kernel_memory(ctx->pcilib, info->ring, flags); - info->ring = NULL; - } - - if (info->pages) { - pcilib_free_kernel_memory(ctx->pcilib, info->pages, flags); - info->pages = NULL; - } - - return 0; -} - -int dma_nwl_write_fragment(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, void *data, size_t *written) { - int err; - size_t pos; - size_t bufnum; - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - pcilib_nwl_engine_description_t *info = ctx->engines + dma; - - err = dma_nwl_start(vctx, dma, PCILIB_DMA_FLAGS_DEFAULT); - if (err) return err; - - if (data) { - for (pos = 0; pos < size; pos += info->page_size) { - int block_size = min2(size - pos, info->page_size); - - bufnum = dma_nwl_get_next_buffer(ctx, info, 1, timeout); - if (bufnum == PCILIB_DMA_BUFFER_INVALID) { - if (written) *written = pos; - return PCILIB_ERROR_TIMEOUT; - } - - void *buf = pcilib_kmem_get_block_ua(ctx->pcilib, info->pages, bufnum); - - pcilib_kmem_sync_block(ctx->pcilib, info->pages, PCILIB_KMEM_SYNC_FROMDEVICE, bufnum); - memcpy(buf, data, block_size); - pcilib_kmem_sync_block(ctx->pcilib, info->pages, PCILIB_KMEM_SYNC_TODEVICE, bufnum); - - err = dma_nwl_push_buffer(ctx, info, block_size, (flags&PCILIB_DMA_FLAG_EOP)&&((pos + block_size) == size), timeout); - if (err) { - if (written) *written = pos; - return err; - } - } - } - - if (written) *written = size; - - if (flags&PCILIB_DMA_FLAG_WAIT) { - bufnum = dma_nwl_get_next_buffer(ctx, info, PCILIB_NWL_DMA_PAGES - 1, timeout); - if (bufnum == PCILIB_DMA_BUFFER_INVALID) return PCILIB_ERROR_TIMEOUT; - } - - return 0; -} - -int dma_nwl_stream_read(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, uintptr_t addr, size_t size, pcilib_dma_flags_t flags, pcilib_timeout_t timeout, pcilib_dma_callback_t cb, void *cbattr) { - int err, ret = PCILIB_STREAMING_REQ_PACKET; - pcilib_timeout_t wait = 0; - size_t res = 0; - size_t bufnum; - size_t bufsize; - - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - int eop; - - pcilib_nwl_engine_description_t *info = ctx->engines + dma; - - err = dma_nwl_start(vctx, dma, PCILIB_DMA_FLAGS_DEFAULT); - if (err) return err; - - do { - switch (ret&PCILIB_STREAMING_TIMEOUT_MASK) { - case PCILIB_STREAMING_CONTINUE: wait = PCILIB_DMA_TIMEOUT; break; - case PCILIB_STREAMING_WAIT: wait = timeout; break; -// case PCILIB_STREAMING_CHECK: wait = 0; break; - } - - bufnum = dma_nwl_wait_buffer(ctx, info, &bufsize, &eop, wait); - if (bufnum == PCILIB_DMA_BUFFER_INVALID) { - return (ret&PCILIB_STREAMING_FAIL)?PCILIB_ERROR_TIMEOUT:0; - } - - // EOP is not respected in IPE Camera - if (ctx->dmactx.ignore_eop) eop = 1; - - pcilib_kmem_sync_block(ctx->pcilib, info->pages, PCILIB_KMEM_SYNC_FROMDEVICE, bufnum); - void *buf = pcilib_kmem_get_block_ua(ctx->pcilib, info->pages, bufnum); - ret = cb(cbattr, (eop?PCILIB_DMA_FLAG_EOP:0), bufsize, buf); - if (ret < 0) return -ret; -// DS: Fixme, it looks like we can avoid calling this for the sake of performance -// pcilib_kmem_sync_block(ctx->pcilib, info->pages, PCILIB_KMEM_SYNC_TODEVICE, bufnum); - dma_nwl_return_buffer(ctx, info); - - res += bufsize; - - } while (ret); - - return 0; -} - -int dma_nwl_wait_completion(nwl_dma_t * ctx, pcilib_dma_engine_t dma, pcilib_timeout_t timeout) { - if (dma_nwl_get_next_buffer(ctx, ctx->engines + dma, PCILIB_NWL_DMA_PAGES - 1, PCILIB_DMA_TIMEOUT) == (PCILIB_NWL_DMA_PAGES - 1)) return 0; - else return PCILIB_ERROR_TIMEOUT; -} - diff --git a/dma/nwl_engine.h b/dma/nwl_engine.h deleted file mode 100644 index f9f3f60..0000000 --- a/dma/nwl_engine.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _PCILIB_DMA_NWL_ENGINE_H -#define _PCILIB_DMA_NWL_ENGINE_H - -int dma_nwl_read_engine_config(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, char *base); -int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma); -int dma_nwl_stop_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma); - -int dma_nwl_wait_completion(nwl_dma_t * ctx, pcilib_dma_engine_t dma, pcilib_timeout_t timeout); - - -#endif /* _PCILIB_DMA_NWL_ENGINE_H */ - diff --git a/dma/nwl_engine_buffers.h b/dma/nwl_engine_buffers.h deleted file mode 100644 index c45c3ca..0000000 --- a/dma/nwl_engine_buffers.h +++ /dev/null @@ -1,412 +0,0 @@ -#define NWL_RING_GET(data, offset) *(uint32_t*)(((char*)(data)) + (offset)) -#define NWL_RING_SET(data, offset, val) *(uint32_t*)(((char*)(data)) + (offset)) = (val) -#define NWL_RING_UPDATE(data, offset, mask, val) *(uint32_t*)(((char*)(data)) + (offset)) = ((*(uint32_t*)(((char*)(data)) + (offset)))&(mask))|(val) - -static int dma_nwl_compute_read_s2c_pointers(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, unsigned char *ring, uint32_t ring_pa) { - uint32_t val; - - char *base = info->base_addr; - - nwl_read_register(val, ctx, base, REG_SW_NEXT_BD); - if ((val < ring_pa)||((val - ring_pa) % PCILIB_NWL_DMA_DESCRIPTOR_SIZE)) { - if (val < ring_pa) pcilib_warning("Inconsistent S2C DMA Ring buffer is found (REG_SW_NEXT_BD register value (%lx) is below start of ring [%lx,%lx])", val, ring_pa, PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - else pcilib_warning("Inconsistent S2C DMA Ring buffer is found (REG_SW_NEXT_BD register value (%zu / %u) is fractal)", val - ring_pa, PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - return PCILIB_ERROR_INVALID_STATE; - } - - info->head = (val - ring_pa) / PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - if (info->head >= PCILIB_NWL_DMA_PAGES) { - pcilib_warning("Inconsistent S2C DMA Ring buffer is found (REG_SW_NEXT_BD register value (%zu) out of range)", info->head); - return PCILIB_ERROR_INVALID_STATE; - } - - nwl_read_register(val, ctx, base, REG_DMA_ENG_NEXT_BD); - if ((val < ring_pa)||((val - ring_pa) % PCILIB_NWL_DMA_DESCRIPTOR_SIZE)) { - if (val < ring_pa) pcilib_warning("Inconsistent S2C DMA Ring buffer is found (REG_DMA_ENG_NEXT_BD register value (%lx) is below start of ring [%lx,%lx])", val, ring_pa, PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - else pcilib_warning("Inconsistent S2C DMA Ring buffer is found (REG_DMA_ENG_NEXT_BD register value (%zu / %u) is fractal)", val - ring_pa, PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - return PCILIB_ERROR_INVALID_STATE; - } - - info->tail = (val - ring_pa) / PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - if (info->tail >= PCILIB_NWL_DMA_PAGES) { - pcilib_warning("Inconsistent S2C DMA Ring buffer is found (REG_DMA_ENG_NEXT_BD register value (%zu) out of range)", info->tail); - return PCILIB_ERROR_INVALID_STATE; - } - -#ifdef DEBUG_NWL - printf("S2C: %lu %lu\n", info->tail, info->head); -#endif /* DEBUG_NWL */ - - return 0; -} - -static int dma_nwl_compute_read_c2s_pointers(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, unsigned char *ring, uint32_t ring_pa) { - uint32_t val; - - char *base = info->base_addr; - - nwl_read_register(val, ctx, base, REG_SW_NEXT_BD); - if ((val < ring_pa)||((val - ring_pa) % PCILIB_NWL_DMA_DESCRIPTOR_SIZE)) { - if (val < ring_pa) pcilib_warning("Inconsistent C2S DMA Ring buffer is found (REG_SW_NEXT_BD register value (%lx) is below start of the ring [%lx,%lx])", val, ring_pa, PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - else pcilib_warning("Inconsistent C2S DMA Ring buffer is found (REG_SW_NEXT_BD register value (%zu / %u) is fractal)", val - ring_pa, PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - return PCILIB_ERROR_INVALID_STATE; - } - - info->head = (val - ring_pa) / PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - if (info->head >= PCILIB_NWL_DMA_PAGES) { - pcilib_warning("Inconsistent C2S DMA Ring buffer is found (REG_SW_NEXT_BD register value (%zu) out of range)", info->head); - return PCILIB_ERROR_INVALID_STATE; - } - - info->tail = info->head + 1; - if (info->tail == PCILIB_NWL_DMA_PAGES) info->tail = 0; - -#ifdef DEBUG_NWL - printf("C2S: %lu %lu\n", info->tail, info->head); -#endif /* DEBUG_NWL */ - - return 0; -} - - -static int dma_nwl_allocate_engine_buffers(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info) { - int err = 0; - - int i; - int preserve = 0; - uint16_t sub_use; - uint32_t val; - uint32_t buf_sz; - uint64_t buf_pa; - pcilib_kmem_reuse_state_t reuse_ring, reuse_pages; - pcilib_kmem_flags_t flags; - pcilib_kmem_type_t type; - - char *base = info->base_addr; - - if (info->pages) return 0; - - // Or bidirectional specified by 0x0|addr, or read 0x0|addr and write 0x80|addr - type = (info->desc.direction == PCILIB_DMA_TO_DEVICE)?PCILIB_KMEM_TYPE_DMA_S2C_PAGE:PCILIB_KMEM_TYPE_DMA_C2S_PAGE; - sub_use = info->desc.addr|((info->desc.direction == PCILIB_DMA_TO_DEVICE)?0x80:0x00); - flags = PCILIB_KMEM_FLAG_REUSE|PCILIB_KMEM_FLAG_EXCLUSIVE|PCILIB_KMEM_FLAG_HARDWARE|(info->preserve?PCILIB_KMEM_FLAG_PERSISTENT:0); - - pcilib_kmem_handle_t *ring = pcilib_alloc_kernel_memory(ctx->pcilib, PCILIB_KMEM_TYPE_CONSISTENT, 1, PCILIB_NWL_DMA_PAGES * PCILIB_NWL_DMA_DESCRIPTOR_SIZE, PCILIB_NWL_ALIGNMENT, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_RING, sub_use), flags); - pcilib_kmem_handle_t *pages = pcilib_alloc_kernel_memory(ctx->pcilib, type, PCILIB_NWL_DMA_PAGES, 0, 0, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_PAGES, sub_use), flags); - - if (!ring||!pages) { - if (pages) pcilib_free_kernel_memory(ctx->pcilib, pages, 0); - if (ring) pcilib_free_kernel_memory(ctx->pcilib, ring, 0); - return PCILIB_ERROR_MEMORY; - } - - reuse_ring = pcilib_kmem_is_reused(ctx->pcilib, ring); - reuse_pages = pcilib_kmem_is_reused(ctx->pcilib, pages); - -// I guess idea here was that we not need to check all that stuff during the second iteration -// which is basicaly true (shall we expect any driver-triggered changes or parallel accesses?) -// but still we need to set preserve flag (and that if we enforcing preservation --start-dma). -// Probably having checks anyway is not harming... -// if (!info->preserve) { - if (reuse_ring == reuse_pages) { - if (reuse_ring & PCILIB_KMEM_REUSE_PARTIAL) pcilib_warning("Inconsistent DMA buffers are found (only part of required buffers is available), reinitializing..."); - else if (reuse_ring & PCILIB_KMEM_REUSE_REUSED) { - if ((reuse_ring & PCILIB_KMEM_REUSE_PERSISTENT) == 0) pcilib_warning("Lost DMA buffers are found (non-persistent mode), reinitializing..."); - else if ((reuse_ring & PCILIB_KMEM_REUSE_HARDWARE) == 0) pcilib_warning("Lost DMA buffers are found (missing HW reference), reinitializing..."); - else { - nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); - - if ((val&DMA_ENG_RUNNING) == 0) pcilib_warning("Lost DMA buffers are found (DMA engine is stopped), reinitializing..."); - else preserve = 1; - } - } - } else pcilib_warning("Inconsistent DMA buffers (modes of ring and page buffers does not match), reinitializing...."); -// } - - - unsigned char *data = (unsigned char*)pcilib_kmem_get_ua(ctx->pcilib, ring); - uint32_t ring_pa = pcilib_kmem_get_pa(ctx->pcilib, ring); - - if (preserve) { - if (info->desc.direction == PCILIB_DMA_FROM_DEVICE) err = dma_nwl_compute_read_c2s_pointers(ctx, info, data, ring_pa); - else err = dma_nwl_compute_read_s2c_pointers(ctx, info, data, ring_pa); - - if (err) preserve = 0; - } - - if (preserve) { - info->reused = 1; - buf_sz = pcilib_kmem_get_block_size(ctx->pcilib, pages, 0); - } else { - info->reused = 0; - - memset(data, 0, PCILIB_NWL_DMA_PAGES * PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - - for (i = 0; i < PCILIB_NWL_DMA_PAGES; i++, data += PCILIB_NWL_DMA_DESCRIPTOR_SIZE) { - buf_pa = pcilib_kmem_get_block_pa(ctx->pcilib, pages, i); - buf_sz = pcilib_kmem_get_block_size(ctx->pcilib, pages, i); - - NWL_RING_SET(data, DMA_BD_NDESC_OFFSET, ring_pa + ((i + 1) % PCILIB_NWL_DMA_PAGES) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE); - NWL_RING_SET(data, DMA_BD_BUFAL_OFFSET, buf_pa&0xFFFFFFFF); - NWL_RING_SET(data, DMA_BD_BUFAH_OFFSET, buf_pa>>32); -#ifdef NWL_GENERATE_DMA_IRQ - NWL_RING_SET(data, DMA_BD_BUFL_CTRL_OFFSET, buf_sz | DMA_BD_INT_ERROR_MASK | DMA_BD_INT_COMP_MASK); -#else /* NWL_GENERATE_DMA_IRQ */ - NWL_RING_SET(data, DMA_BD_BUFL_CTRL_OFFSET, buf_sz); -#endif /* NWL_GENERATE_DMA_IRQ */ - } - - val = ring_pa; - nwl_write_register(val, ctx, base, REG_DMA_ENG_NEXT_BD); - nwl_write_register(val, ctx, base, REG_SW_NEXT_BD); - - info->head = 0; - info->tail = 0; - } - - info->ring = ring; - info->pages = pages; - info->page_size = buf_sz; - info->ring_size = PCILIB_NWL_DMA_PAGES; - - return 0; -} - - -static size_t dma_nwl_clean_buffers(nwl_dma_t * ctx, pcilib_nwl_engine_description_t *info) { - size_t res = 0; - uint32_t status; - - unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring); - ring += info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - -next_buffer: - status = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET)&DMA_BD_STATUS_MASK; -// control = NWL_RING_GET(ring, DMA_BD_BUFL_CTRL_OFFSET)&DMA_BD_CTRL_MASK; - - if (status & DMA_BD_ERROR_MASK) { - pcilib_error("NWL DMA Engine reported error in ring descriptor"); - return (size_t)-1; - } - - if (status & DMA_BD_SHORT_MASK) { - pcilib_error("NWL DMA Engine reported short error"); - return (size_t)-1; - } - - if (status & DMA_BD_COMP_MASK) { - info->tail++; - if (info->tail == info->ring_size) { - ring -= (info->tail - 1) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - info->tail = 0; - } else { - ring += PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - } - - res++; - - if (info->tail != info->head) goto next_buffer; - } - -// printf("====> Cleaned: %i\n", res); - return res; -} - - -static size_t dma_nwl_get_next_buffer(nwl_dma_t * ctx, pcilib_nwl_engine_description_t *info, size_t n_buffers, pcilib_timeout_t timeout) { - struct timeval start, cur; - - size_t res, n = 0; - size_t head; - - for (head = info->head; (((head + 1)%info->ring_size) != info->tail)&&(n < n_buffers); head++, n++); - if (n == n_buffers) return info->head; - - gettimeofday(&start, NULL); - - res = dma_nwl_clean_buffers(ctx, info); - if (res == (size_t)-1) return PCILIB_DMA_BUFFER_INVALID; - else n += res; - - - while (n < n_buffers) { - if (timeout != PCILIB_TIMEOUT_INFINITE) { - gettimeofday(&cur, NULL); - if (((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) > timeout) break; - } - - usleep (10); - - res = dma_nwl_clean_buffers(ctx, info); - if (res == (size_t)-1) return PCILIB_DMA_BUFFER_INVALID; - else if (res > 0) { - gettimeofday(&start, NULL); - n += res; - } - } - - if (n < n_buffers) return PCILIB_DMA_BUFFER_INVALID; - - return info->head; -} - -static int dma_nwl_push_buffer(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, size_t size, int eop, pcilib_timeout_t timeout) { - int flags = 0; - - uint32_t val; - unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring); - uint32_t ring_pa = pcilib_kmem_get_pa(ctx->pcilib, info->ring); - - ring += info->head * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - - - if (!info->writting) { - flags |= DMA_BD_SOP_MASK; - info->writting = 1; - } - if (eop) { - flags |= DMA_BD_EOP_MASK; - info->writting = 0; - } - - NWL_RING_SET(ring, DMA_BD_BUFL_CTRL_OFFSET, size|flags); - NWL_RING_SET(ring, DMA_BD_BUFL_STATUS_OFFSET, size); - - info->head++; - if (info->head == info->ring_size) info->head = 0; - - val = ring_pa + info->head * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - nwl_write_register(val, ctx, info->base_addr, REG_SW_NEXT_BD); - - return 0; -} - - -static size_t dma_nwl_wait_buffer(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info, size_t *size, int *eop, pcilib_timeout_t timeout) { - struct timeval start, cur; - uint32_t status_size, status; - - unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring); - - ring += info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - - gettimeofday(&start, NULL); - - do { - status_size = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET); - status = status_size & DMA_BD_STATUS_MASK; - - if (status & DMA_BD_ERROR_MASK) { - pcilib_error("NWL DMA Engine reported error in ring descriptor"); - return (size_t)-1; - } - - if (status & DMA_BD_COMP_MASK) { - if (status & DMA_BD_EOP_MASK) *eop = 1; - else *eop = 0; - - *size = status_size & DMA_BD_BUFL_MASK; - -/* - if (mrd) { - if ((info->tail + 1) == info->ring_size) ring -= info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - else ring += PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - *mrd = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET)&DMA_BD_COMP_MASK; - } -*/ - - return info->tail; - } - - usleep(10); - gettimeofday(&cur, NULL); - } while ((timeout == PCILIB_TIMEOUT_INFINITE)||(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < timeout)); - - return (size_t)-1; -} - -/* - // This function is not used now, but we may need it in the future -static int dma_nwl_is_overflown(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info) { - uint32_t status; - unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring); - if (info->tail > 0) ring += (info->tail - 1) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - else ring += (info->ring_size - 1) * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - - status = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET); - return status&DMA_BD_COMP_MASK?1:0; -} -*/ - -static int dma_nwl_return_buffer(nwl_dma_t *ctx, pcilib_nwl_engine_description_t *info) { - uint32_t val; - - unsigned char *ring = pcilib_kmem_get_ua(ctx->pcilib, info->ring); - uint32_t ring_pa = pcilib_kmem_get_pa(ctx->pcilib, info->ring); - size_t bufsz = pcilib_kmem_get_block_size(ctx->pcilib, info->pages, info->tail); - - ring += info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - -#ifdef NWL_GENERATE_DMA_IRQ - NWL_RING_SET(ring, DMA_BD_BUFL_CTRL_OFFSET, bufsz | DMA_BD_INT_ERROR_MASK | DMA_BD_INT_COMP_MASK); -#else /* NWL_GENERATE_DMA_IRQ */ - NWL_RING_SET(ring, DMA_BD_BUFL_CTRL_OFFSET, bufsz); -#endif /* NWL_GENERATE_DMA_IRQ */ - - NWL_RING_SET(ring, DMA_BD_BUFL_STATUS_OFFSET, 0); - - val = ring_pa + info->tail * PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - nwl_write_register(val, ctx, info->base_addr, REG_SW_NEXT_BD); - - info->tail++; - if (info->tail == info->ring_size) info->tail = 0; - - return 0; -} - -int dma_nwl_get_status(pcilib_dma_context_t *vctx, pcilib_dma_engine_t dma, pcilib_dma_engine_status_t *status, size_t n_buffers, pcilib_dma_buffer_status_t *buffers) { - size_t i; - uint32_t bstatus; - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - pcilib_nwl_engine_description_t *info = ctx->engines + dma; - unsigned char *ring = (unsigned char*)pcilib_kmem_get_ua(ctx->pcilib, info->ring); - - - if (!status) return -1; - - status->started = info->started; - status->ring_size = info->ring_size; - status->buffer_size = info->page_size; - status->ring_tail = info->tail; - - if (info->desc.direction == PCILIB_DMA_FROM_DEVICE) { - size_t pos = 0; - for (i = 0; i < info->ring_size; i++) { - pos = status->ring_tail + i; - if (pos >= info->ring_size) pos -= info->ring_size; - - bstatus = NWL_RING_GET(ring + pos * PCILIB_NWL_DMA_DESCRIPTOR_SIZE, DMA_BD_BUFL_STATUS_OFFSET); - if ((bstatus&(DMA_BD_ERROR_MASK|DMA_BD_COMP_MASK)) == 0) break; - } - status->ring_head = pos; - } else { - status->ring_head = info->head; - } - - - if (buffers) { - for (i = 0; (i < info->ring_size)&&(i < n_buffers); i++) { - bstatus = NWL_RING_GET(ring, DMA_BD_BUFL_STATUS_OFFSET); - - buffers[i].error = bstatus & (DMA_BD_ERROR_MASK/*|DMA_BD_SHORT_MASK*/); - buffers[i].used = bstatus & DMA_BD_COMP_MASK; - buffers[i].size = bstatus & DMA_BD_BUFL_MASK; - buffers[i].first = bstatus & DMA_BD_SOP_MASK; - buffers[i].last = bstatus & DMA_BD_EOP_MASK; - - ring += PCILIB_NWL_DMA_DESCRIPTOR_SIZE; - } - } - - return 0; -} diff --git a/dma/nwl_irq.c b/dma/nwl_irq.c deleted file mode 100644 index e71c76a..0000000 --- a/dma/nwl_irq.c +++ /dev/null @@ -1,119 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/time.h> - -#include "pcilib.h" - -#include "pci.h" -#include "error.h" -#include "tools.h" - -#include "nwl_private.h" -#include "nwl_defines.h" - -int dma_nwl_init_irq(nwl_dma_t *ctx, uint32_t val) { - if (val&(DMA_INT_ENABLE|DMA_USER_INT_ENABLE)) { - if (val&DMA_INT_ENABLE) ctx->irq_preserve |= PCILIB_DMA_IRQ; - if (val&DMA_USER_INT_ENABLE) ctx->irq_preserve |= PCILIB_EVENT_IRQ; - } - - ctx->irq_started = 1; - return 0; -} - -int dma_nwl_free_irq(nwl_dma_t *ctx) { - if (ctx->irq_started) { - dma_nwl_disable_irq((pcilib_dma_context_t*)ctx, 0); - if (ctx->irq_preserve) dma_nwl_enable_irq((pcilib_dma_context_t*)ctx, ctx->irq_preserve, 0); - ctx->irq_enabled = 0; - ctx->irq_started = 0; - } - return 0; -} - -int dma_nwl_enable_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t type, pcilib_dma_flags_t flags) { - uint32_t val; - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - if (flags&PCILIB_DMA_FLAG_PERSISTENT) ctx->irq_preserve |= type; - - if ((ctx->irq_enabled&type) == type) return 0; - - type |= ctx->irq_enabled; - - nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS); - if (!ctx->irq_started) dma_nwl_init_irq(ctx, val); - - val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE); - nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS); - - pcilib_clear_irq(ctx->pcilib, NWL_DMA_IRQ_SOURCE); - - if (type & PCILIB_DMA_IRQ) val |= DMA_INT_ENABLE; - if (type & PCILIB_EVENT_IRQ) val |= DMA_USER_INT_ENABLE; - nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS); - - ctx->irq_enabled = type; - - return 0; -} - - -int dma_nwl_disable_irq(pcilib_dma_context_t *vctx, pcilib_dma_flags_t flags) { - uint32_t val; - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - ctx->irq_enabled = 0; - - nwl_read_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS); - if (!ctx->irq_started) dma_nwl_init_irq(ctx, val); - val &= ~(DMA_INT_ENABLE|DMA_USER_INT_ENABLE); - nwl_write_register(val, ctx, ctx->base_addr, REG_DMA_CTRL_STATUS); - - if (flags&PCILIB_DMA_FLAG_PERSISTENT) ctx->irq_preserve = 0; - - return 0; -} - - -int dma_nwl_enable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { - uint32_t val; - - dma_nwl_enable_irq((pcilib_dma_context_t*)ctx, PCILIB_DMA_IRQ, 0); - - nwl_read_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS); - val |= (DMA_ENG_INT_ENABLE); - nwl_write_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS); - - return 0; -} - -int dma_nwl_disable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { - uint32_t val; - - nwl_read_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS); - val &= ~(DMA_ENG_INT_ENABLE); - nwl_write_register(val, ctx, ctx->engines[dma].base_addr, REG_DMA_ENG_CTRL_STATUS); - - return 0; -} - -int dma_nwl_acknowledge_irq(pcilib_dma_context_t *vctx, pcilib_irq_type_t irq_type, pcilib_irq_source_t irq_source) { - uint32_t val; - - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - pcilib_nwl_engine_description_t *info = ctx->engines + irq_source; - - if (irq_type != PCILIB_DMA_IRQ) return PCILIB_ERROR_NOTSUPPORTED; - if (irq_source >= ctx->n_engines) return PCILIB_ERROR_NOTAVAILABLE; - - nwl_read_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); - if (val & DMA_ENG_INT_ACTIVE_MASK) { - val |= DMA_ENG_ALLINT_MASK; - nwl_write_register(val, ctx, info->base_addr, REG_DMA_ENG_CTRL_STATUS); - } - - return 0; -} diff --git a/dma/nwl_irq.h b/dma/nwl_irq.h deleted file mode 100644 index 811b632..0000000 --- a/dma/nwl_irq.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _PCILIB_NWL_IRQ_H -#define _PCILIB_NWL_IRQ_H - -int dma_nwl_init_irq(nwl_dma_t *ctx, uint32_t val); -int dma_nwl_free_irq(nwl_dma_t *ctx); - -int dma_nwl_enable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma); -int dma_nwl_disable_engine_irq(nwl_dma_t *ctx, pcilib_dma_engine_t dma); - -#endif /* _PCILIB_NWL_IRQ_H */ diff --git a/dma/nwl_loopback.c b/dma/nwl_loopback.c deleted file mode 100644 index 381a462..0000000 --- a/dma/nwl_loopback.c +++ /dev/null @@ -1,255 +0,0 @@ -#define _BSD_SOURCE -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/time.h> - -#include "pci.h" -#include "pcilib.h" -#include "error.h" -#include "tools.h" -#include "nwl_private.h" - -#include "nwl_defines.h" - -#define NWL_BUG_EXTRA_DATA - - -int dma_nwl_start_loopback(nwl_dma_t *ctx, pcilib_dma_direction_t direction, size_t packet_size) { - uint32_t val; - - ctx->loopback_started = 1; - dma_nwl_stop_loopback(ctx); - - val = packet_size; - nwl_write_register(val, ctx, ctx->base_addr, PKT_SIZE_ADDRESS); - - if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) { - switch (direction) { - case PCILIB_DMA_BIDIRECTIONAL: - val = LOOPBACK; - nwl_write_register(val, ctx, ctx->base_addr, TX_CONFIG_ADDRESS); - break; - case PCILIB_DMA_TO_DEVICE: - return -1; - case PCILIB_DMA_FROM_DEVICE: - val = PKTGENR; - nwl_write_register(val, ctx, ctx->base_addr, RX_CONFIG_ADDRESS); - break; - } - } - - ctx->loopback_started = 1; - - return 0; -} - -int dma_nwl_stop_loopback(nwl_dma_t *ctx) { - uint32_t val = 0; - - if (!ctx->loopback_started) return 0; - - /* Stop in any case, otherwise we can have problems in benchmark due to - engine initialized in previous run, and benchmark is only actual usage. - Otherwise, we should detect current loopback status during initialization */ - - if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) { - nwl_write_register(val, ctx, ctx->base_addr, TX_CONFIG_ADDRESS); - nwl_write_register(val, ctx, ctx->base_addr, RX_CONFIG_ADDRESS); - } - - ctx->loopback_started = 0; - - return 0; -} - -double dma_nwl_benchmark(pcilib_dma_context_t *vctx, pcilib_dma_engine_addr_t dma, uintptr_t addr, size_t size, size_t iterations, pcilib_dma_direction_t direction) { - int iter, i; - int err; - size_t bytes, rbytes; - uint32_t *buf, *cmp; - const char *error = NULL; - size_t packet_size, blocks; - - size_t us = 0; - struct timeval start, cur; - - nwl_dma_t *ctx = (nwl_dma_t*)vctx; - - pcilib_dma_engine_t readid = pcilib_find_dma_by_addr(ctx->pcilib, PCILIB_DMA_FROM_DEVICE, dma); - pcilib_dma_engine_t writeid = pcilib_find_dma_by_addr(ctx->pcilib, PCILIB_DMA_TO_DEVICE, dma); - - if (size%sizeof(uint32_t)) size = 1 + size / sizeof(uint32_t); - else size /= sizeof(uint32_t); - - // Not supported - if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) { - if (direction == PCILIB_DMA_TO_DEVICE) return -1.; - } -// else if ((direction == PCILIB_DMA_FROM_DEVICE)&&(ctx->type != PCILIB_DMA_MODIFICATION_DEFAULT)) return -1.; - - // Stop Generators and drain old data - if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) dma_nwl_stop_loopback(ctx); -// dma_nwl_stop_engine(ctx, readid); // DS: replace with something better - - __sync_synchronize(); - - err = pcilib_skip_dma(ctx->pcilib, readid); - if (err) { - pcilib_error("Can't start benchmark, devices continuously writes unexpected data using DMA engine"); - return -1; - } - -#ifdef NWL_GENERATE_DMA_IRQ - dma_nwl_enable_engine_irq(ctx, readid); - dma_nwl_enable_engine_irq(ctx, writeid); -#endif /* NWL_GENERATE_DMA_IRQ */ - - if (size * sizeof(uint32_t) > NWL_MAX_PACKET_SIZE) { - packet_size = NWL_MAX_PACKET_SIZE; - blocks = (size * sizeof(uint32_t)) / packet_size + (((size*sizeof(uint32_t))%packet_size)?1:0); - } else { - packet_size = size * sizeof(uint32_t); - blocks = 1; - } - - dma_nwl_start_loopback(ctx, direction, packet_size); - - // Allocate memory and prepare data - buf = malloc(blocks * packet_size * sizeof(uint32_t)); - cmp = malloc(blocks * packet_size * sizeof(uint32_t)); - if ((!buf)||(!cmp)) { - if (buf) free(buf); - if (cmp) free(cmp); - return -1; - } - - if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) { - pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e5); - usleep(100000); - pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e1); - - // This way causes more problems with garbage - //pcilib_write_register(ctx->pcilib, NULL, "control", 0x3e1); - } - - // Benchmark - for (iter = 0; iter < iterations; iter++) { - memset(cmp, 0x13 + iter, size * sizeof(uint32_t)); - - if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) { - pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e1); - } - - if ((direction&PCILIB_DMA_TO_DEVICE)||(ctx->type != PCILIB_DMA_MODIFICATION_DEFAULT)) { - memcpy(buf, cmp, size * sizeof(uint32_t)); - - if (direction&PCILIB_DMA_TO_DEVICE) { - gettimeofday(&start, NULL); - } - - err = pcilib_write_dma(ctx->pcilib, writeid, addr, size * sizeof(uint32_t), buf, &bytes); - if ((err)||(bytes != size * sizeof(uint32_t))) { - error = "Write failed"; - break; - } - - if (direction&PCILIB_DMA_TO_DEVICE) { - // wait written - if (direction == PCILIB_DMA_TO_DEVICE) { - dma_nwl_wait_completion(ctx, writeid, PCILIB_DMA_TIMEOUT); - } - gettimeofday(&cur, NULL); - us += ((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)); - } - } - - if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) { - pcilib_write_register(ctx->pcilib, NULL, "control", 0x3e1); - } - - memset(buf, 0, size * sizeof(uint32_t)); - - if (direction&PCILIB_DMA_FROM_DEVICE) { - gettimeofday(&start, NULL); - } - - for (i = 0, bytes = 0; i < blocks; i++) { -#ifdef NWL_BUG_EXTRA_DATA - retry: -#endif - - err = pcilib_read_dma(ctx->pcilib, readid, addr, packet_size * sizeof(uint32_t), buf + (bytes>>2), &rbytes); - if ((err)||(rbytes%sizeof(uint32_t))) { - break; - } -#ifdef NWL_BUG_EXTRA_DATA - else if (rbytes == 8) { - goto retry; - } -#endif - bytes += rbytes; - } - - if (direction&PCILIB_DMA_FROM_DEVICE) { - gettimeofday(&cur, NULL); - us += ((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)); - } -#ifdef NWL_BUG_EXTRA_DATA - if ((err)||((bytes != size * sizeof(uint32_t))&&((bytes - 8) != size * sizeof(uint32_t)))) { -#else - if ((err)||(bytes != size * sizeof(uint32_t))) { -#endif - printf("Expected: %zu bytes, but %zu read, error: %i\n", size * sizeof(uint32_t), bytes, err); - error = "Read failed"; - break; - } - -#ifndef NWL_BUG_EXTRA_DATA - if (direction == PCILIB_DMA_BIDIRECTIONAL) { - if (memcmp(buf, cmp, size * sizeof(uint32_t))) { - for (i = 0; i < size; i++) - if (buf[i] != cmp[i]) break; - - bytes = i; - printf("Expected: *0x%lx, Written at dword %lu:", 0x13 + iter, bytes); - for (; (i < size)&&(i < (bytes + 16)); i++) { - if (((i - bytes)%8)==0) printf("\n"); - printf("% 10lx", buf[i]); - } - printf("\n"); - - error = "Written and read values does not match"; - break; - } - } -#endif - } - - if (ctx->type == PCILIB_NWL_MODIFICATION_IPECAMERA) { - pcilib_write_register(ctx->pcilib, NULL, "control", 0x1e1); - } - - if (error) { - pcilib_warning("%s at iteration %i, error: %i, bytes: %zu", error, iter, err, bytes); - } - -#ifdef NWL_GENERATE_DMA_IRQ - dma_nwl_disable_engine_irq(ctx, writeid); - dma_nwl_disable_engine_irq(ctx, readid); -#endif /* NWL_GENERATE_DMA_IRQ */ - - dma_nwl_stop_loopback(ctx); - - __sync_synchronize(); - - if (direction == PCILIB_DMA_FROM_DEVICE) { - pcilib_skip_dma(ctx->pcilib, readid); - } - - free(cmp); - free(buf); - - return /*error?-1:*/(1. * size * sizeof(uint32_t) * iterations * 1000000) / (1024. * 1024. * us); -} diff --git a/dma/nwl_loopback.h b/dma/nwl_loopback.h deleted file mode 100644 index 63c8446..0000000 --- a/dma/nwl_loopback.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _PCILIB_NWL_LOOPBACK_H -#define _PCILIB_NWL_LOOPBACK_H - -int dma_nwl_start_loopback(nwl_dma_t *ctx, pcilib_dma_direction_t direction, size_t packet_size); -int dma_nwl_stop_loopback(nwl_dma_t *ctx); - -#endif /* _PCILIB_NWL_LOOPBACK_H */ diff --git a/dma/nwl_private.h b/dma/nwl_private.h deleted file mode 100644 index 756e6ca..0000000 --- a/dma/nwl_private.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef _PCILIB_DMA_NWL_PRIVATE_H -#define _PCILIB_DMA_NWL_PRIVATE_H - -typedef struct nwl_dma_s nwl_dma_t; -typedef struct pcilib_nwl_engine_description_s pcilib_nwl_engine_description_t; - -#define NWL_DMA_IRQ_SOURCE 0 - -#define NWL_XAUI_ENGINE 0 -#define NWL_XRAWDATA_ENGINE 1 -#define NWL_MAX_PACKET_SIZE 4096 //16384 -//#define NWL_GENERATE_DMA_IRQ - -#define PCILIB_NWL_ALIGNMENT 64 // in bytes -#define PCILIB_NWL_DMA_DESCRIPTOR_SIZE 64 // in bytes -#define PCILIB_NWL_DMA_PAGES 256 // 1024 - -//#define DEBUG_HARDWARE -//#define DEBUG_NWL - -#include "nwl.h" -#include "nwl_irq.h" -#include "nwl_register.h" -#include "nwl_engine.h" -#include "nwl_loopback.h" - -#define nwl_read_register(var, ctx, base, reg) pcilib_datacpy(&var, base + reg, 4, 1, ctx->dma_bank->raw_endianess) -#define nwl_write_register(var, ctx, base, reg) pcilib_datacpy(base + reg, &var, 4, 1, ctx->dma_bank->raw_endianess) - -struct pcilib_nwl_engine_description_s { - pcilib_dma_engine_description_t desc; - char *base_addr; - - size_t ring_size, page_size; - size_t head, tail; - pcilib_kmem_handle_t *ring; - pcilib_kmem_handle_t *pages; - - int started; /**< indicates that DMA buffers are initialized and reading is allowed */ - int writting; /**< indicates that we are in middle of writting packet */ - int reused; /**< indicates that DMA was found intialized, buffers were reused, and no additional initialization is needed */ - int preserve; /**< indicates that DMA should not be stopped during clean-up */ -}; - - -struct nwl_dma_s { - struct pcilib_dma_context_s dmactx; - - pcilib_t *pcilib; - - pcilib_dma_modification_t type; - - pcilib_register_bank_description_t *dma_bank; - char *base_addr; - - pcilib_irq_type_t irq_enabled; /**< indicates that IRQs are enabled */ - pcilib_irq_type_t irq_preserve; /**< indicates that IRQs should not be disabled during clean-up */ - int started; /**< indicates that DMA subsystem is initialized and DMA engine can start */ - int irq_started; /**< indicates that IRQ subsystem is initialized (detecting which types should be preserverd) */ - int loopback_started; /**< indicates that benchmarking subsystem is initialized */ - - pcilib_dma_engine_t n_engines; - pcilib_nwl_engine_description_t engines[PCILIB_MAX_DMA_ENGINES + 1]; -}; - - -#endif /* _PCILIB_DMA_NWL_PRIVATE_H */ diff --git a/dma/nwl_register.c b/dma/nwl_register.c deleted file mode 100644 index 6a3771a..0000000 --- a/dma/nwl_register.c +++ /dev/null @@ -1,77 +0,0 @@ -#define _PCILIB_NWL_REGISTER_C - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/time.h> - -#include "pcilib.h" - -#include "pci.h" -#include "error.h" -#include "tools.h" - -#include "nwl_private.h" -#include "nwl_register.h" - -int nwl_add_registers(nwl_dma_t *ctx) { - int err; - size_t n, i, j; - int length; - const char *names[NWL_MAX_DMA_ENGINE_REGISTERS]; - uintptr_t addr[NWL_MAX_DMA_ENGINE_REGISTERS]; - - // We don't want DMA registers - if (pcilib_find_bank_by_addr(ctx->pcilib, PCILIB_REGISTER_BANK_DMA) == PCILIB_REGISTER_BANK_INVALID) return 0; - - err = pcilib_add_registers(ctx->pcilib, 0, nwl_dma_registers); - if (err) return err; - - if (ctx->type == PCILIB_DMA_MODIFICATION_DEFAULT) { - err = pcilib_add_registers(ctx->pcilib, 0, nwl_xrawdata_registers); - if (err) return err; - } - - - for (n = 0; nwl_dma_engine_registers[n].bits; n++) { - names[n] = nwl_dma_engine_registers[n].name; - addr[n] = nwl_dma_engine_registers[n].addr; - } - - if (ctx->n_engines > 9) length = 2; - else length = 1; - - - for (i = 0; i < ctx->n_engines; i++) { - for (j = 0; nwl_dma_engine_registers[j].bits; j++) { - const char *direction; - nwl_dma_engine_registers[j].name = nwl_dma_engine_register_names[i * NWL_MAX_DMA_ENGINE_REGISTERS + j]; - nwl_dma_engine_registers[j].addr = addr[j] + (ctx->engines[i].base_addr - ctx->base_addr); -// printf("%lx %lx\n", (ctx->engines[i].base_addr - ctx->base_addr), nwl_dma_engine_registers[j].addr); - - switch (ctx->engines[i].desc.direction) { - case PCILIB_DMA_FROM_DEVICE: - direction = "r"; - break; - case PCILIB_DMA_TO_DEVICE: - direction = "w"; - break; - default: - direction = ""; - } - - sprintf((char*)nwl_dma_engine_registers[j].name, names[j], length, ctx->engines[i].desc.addr, direction); - } - - err = pcilib_add_registers(ctx->pcilib, n, nwl_dma_engine_registers); - if (err) return err; - } - - for (n = 0; nwl_dma_engine_registers[n].bits; n++) { - nwl_dma_engine_registers[n].name = names[n]; - nwl_dma_engine_registers[n].addr = addr[n]; - } - - return 0; -} diff --git a/dma/nwl_register.h b/dma/nwl_register.h deleted file mode 100644 index a71942b..0000000 --- a/dma/nwl_register.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _PCILIB_NWL_REGISTERS_H -#define _PCILIB_NWL_REGISTERS_H - -#ifdef _PCILIB_NWL_REGISTER_C - // DMA -static pcilib_register_description_t nwl_dma_registers[] = { - {0x4000, 0, 32, 0, 0x00000011, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_control_and_status", ""}, - {0x4000, 0, 1, 0, 0x00000011, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_enable", ""}, - {0x4000, 1, 1, 0, 0x00000011, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_active", ""}, - {0x4000, 2, 1, 0, 0x00000011, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_pending", ""}, - {0x4000, 3, 1, 0, 0x00000011, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_interrupt_mode", ""}, - {0x4000, 4, 1, 0, 0x00000011, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_user_interrupt_enable", ""}, - {0x4000, 5, 1, 0, 0x00000011, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_user_interrupt_active", ""}, - {0x4000, 16, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_s2c_interrupt_status", ""}, - {0x4000, 24, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_c2s_interrupt_status", ""}, - {0x8000, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_design_version", ""}, - {0x8000, 0, 4, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_subversion_number", ""}, - {0x8000, 4, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_version_number", ""}, - {0x8000, 28, 4, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_targeted_device", ""}, - {0x8200, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_transmit_utilization", ""}, - {0x8200, 0, 2, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_transmit_sample_count", ""}, - {0x8200, 2, 30, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_transmit_dword_count", ""}, - {0x8204, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_receive_utilization", ""}, - {0x8004, 0, 2, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_receive_sample_count", ""}, - {0x8004, 2, 30, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_receive_dword_count", ""}, - {0x8208, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_mwr", ""}, - {0x8008, 0, 2, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_mwr_sample_count", ""}, - {0x8008, 2, 30, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_mwr_dword_count", ""}, - {0x820C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_cpld", ""}, - {0x820C, 0, 2, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_cpld_sample_count", ""}, - {0x820C, 2, 30, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma_cpld_dword_count", ""}, - {0x8210, 0, 12, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_cpld", ""}, - {0x8214, 0, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_cplh", ""}, - {0x8218, 0, 12, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_npd", ""}, - {0x821C, 0, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_nph", ""}, - {0x8220, 0, 12, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_pd", ""}, - {0x8224, 0, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_init_fc_ph", ""}, - {0, 0, 0, 0, 0x00000000, 0, 0, 0, NULL, NULL} -}; - - // DMA Engine Registers -#define NWL_MAX_DMA_ENGINE_REGISTERS 64 -#define NWL_MAX_REGISTER_NAME 128 -static char nwl_dma_engine_register_names[PCILIB_MAX_DMA_ENGINES * NWL_MAX_DMA_ENGINE_REGISTERS][NWL_MAX_REGISTER_NAME]; -static pcilib_register_description_t nwl_dma_engine_registers[] = { - {0x0000, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_engine_capabilities", ""}, - {0x0000, 0, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_present", ""}, - {0x0000, 1, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_direction", ""}, - {0x0000, 4, 2, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_type", ""}, - {0x0000, 8, 8, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_number", ""}, - {0x0000, 24, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_max_buffer_size", ""}, - {0x0004, 0, 32, 0, 0x0000C100, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_engine_control", ""}, - {0x0004, 0, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_interrupt_enable", ""}, - {0x0004, 1, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_interrupt_active", ""}, - {0x0004, 2, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_complete", ""}, - {0x0004, 3, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_alignment_error", ""}, - {0x0004, 4, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_fetch_error", ""}, - {0x0004, 5, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sw_abort_error", ""}, - {0x0004, 8, 1, 0, 0x0000C100, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_enable", ""}, - {0x0004, 10, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_running", ""}, - {0x0004, 11, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_waiting", ""}, - {0x0004, 14, 1, 0, 0x0000C100, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_reset_request", ""}, - {0x0004, 15, 1, 0, 0x0000C100, PCILIB_REGISTER_W , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_reset", ""}, - {0x0008, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_next_descriptor", ""}, - {0x000C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sw_descriptor", ""}, - {0x0010, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_last_descriptor", ""}, - {0x0014, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_active_time", ""}, - {0x0018, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_wait_time", ""}, - {0x001C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_counter", ""}, - {0x001C, 0, 2, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sample_count", ""}, - {0x001C, 2, 30, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_dword_count", ""}, - {0, 0, 0, 0, 0x00000000, 0, 0, 0, NULL, NULL} -}; - -/* - // XAUI registers -static pcilib_register_description_t nwl_xaui_registers[] = { - {0, 0, 0, 0, 0, 0, 0, NULL, NULL} -}; -*/ - - // XRAWDATA registers -static pcilib_register_description_t nwl_xrawdata_registers[] = { - {0x9100, 0, 1, 0, 0x00000000, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_enable_generator", ""}, - {0x9104, 0, 16, 0, 0x00000000, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_packet_length", ""}, - {0x9108, 0, 2, 0, 0x00000003, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_control", ""}, - {0x9108, 0, 1, 0, 0x00000003, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "xrawdata_enable_checker", ""}, - {0x9108, 1, 1, 0, 0x00000003, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "xrawdata_enable_loopback", ""}, - {0x910C, 0, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_data_mistmatch", ""}, - {0, 0, 0, 0, 0x00000000, 0, 0, 0, NULL, NULL} -}; - -#endif /* _PCILIB_NWL_REGISTERS_C */ - -int nwl_add_registers(nwl_dma_t *ctx); - -#endif /* _PCILIB_NWL_REGISTERS_H */ |