Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | Implement DMA access synchronization in the driver | Suren A. Chilingaryan | 2011-07-16 | 2 | -3/+6 | |
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* | First iteration of work to preserve DMA state between executions | Suren A. Chilingaryan | 2011-07-14 | 6 | -201/+228 | |
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* | Support modifications of DMA engine and allow DMA customizations by Event engine | Suren A. Chilingaryan | 2011-07-14 | 5 | -89/+89 | |
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* | Few fixes | Suren A. Chilingaryan | 2011-07-12 | 2 | -7/+18 | |
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* | Separate NWL loopback code, provide DMA start/stop interfaces | Suren A. Chilingaryan | 2011-07-12 | 8 | -77/+136 | |
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* | Another reorganization of NWL sources | Suren A. Chilingaryan | 2011-07-12 | 6 | -285/+301 | |
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* | Provide IRQ enable/disable call | Suren A. Chilingaryan | 2011-07-12 | 5 | -18/+121 | |
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* | Suppport DMA modes in console application (not functional yet) | Suren A. Chilingaryan | 2011-07-12 | 4 | -12/+17 | |
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* | Few fixes | Suren A. Chilingaryan | 2011-07-12 | 1 | -5/+21 | |
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* | Fix compilation issues | Suren A. Chilingaryan | 2011-07-11 | 1 | -5/+5 | |
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* | Reorganization of NWL engine, step 1 | Suren A. Chilingaryan | 2011-07-11 | 4 | -128/+171 | |
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* | Wait for the completion of DMA operations during writes | Suren A. Chilingaryan | 2011-07-11 | 3 | -321/+335 | |
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* | IRQ support in NWL DMA engine | Suren A. Chilingaryan | 2011-07-11 | 7 | -129/+244 | |
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* | Support dynamic registers, support register offsets and multiregisters ↵ | Suren A. Chilingaryan | 2011-07-09 | 2 | -8/+161 | |
| | | | | (bitmasks), list NWL DMA registers | |||||
* | Add some check to verify if NWL DMA engine have been successfully initialized | Suren A. Chilingaryan | 2011-07-08 | 1 | -5/+3 | |
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* | Support alignments in kmem allocation | Suren A. Chilingaryan | 2011-07-06 | 1 | -1/+1 | |
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* | A bit of renaming | Suren A. Chilingaryan | 2011-07-06 | 2 | -12/+12 | |
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* | Define addresses of NWL engines | root | 2011-07-04 | 1 | -1/+3 | |
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* | North West Logick DMA implementation | root | 2011-07-04 | 3 | -104/+711 | |
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* | DMA engine initialization and basic intrastructure for DMA read/write | root | 2011-06-18 | 2 | -1/+102 | |
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* | Enumerate DMA engines | root | 2011-06-17 | 2 | -0/+208 | |